LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY encoder_tb IS
END ENTITY encoder_tb;

ARCHITECTURE structural OF encodertb IS
    COMPONENT encoder IS
        PORT (
            clk : IN std_logic; -- clock
            reset : IN std_logic; -- async reset
            start : IN std_logic; -- start signal
            x : IN std_logic_vector (7 DOWNTO 0); -- input
            y : OUT std_logic_vector (7 DOWNTO 0); -- output
            ready : OUT std_logic -- ready signal
        );
    END COMPONENT encoder;

    SIGNAL clk, reset : std_logic;
    SIGNAL start : std_logic;
    SIGNAL ready : std_logic;
    SIGNAL x : std_logic_vector(7 DOWNTO 0);
    SIGNAL y : std_logic_vector(7 DOWNTO 0);

BEGIN
    lbl1 : encoder PORT MAP(
        clk => clk,
        reset => reset,
        start => start,
        ready => ready,
        x => x,
        y => y
    );

    -- 20 ns = 50 MHz
    clk <= '0' AFTER 0 ns,
        '1' AFTER 10 ns WHEN clk /= '1' ELSE
        '0' AFTER 10 ns;

    reset <= '1' AFTER 0 ns,
        '0' AFTER 40 ns;

    start <= '1' AFTER 0 ns,
        '0' AFTER 100 ns;

    x <= "10101101" AFTER 0 ns;

END ARCHITECTURE structural;