library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY dek_4_16e IS PORT (
  E : IN Std_Logic;
  A : IN Std_Logic_Vector(3 downto 0);
  Y : OUT Std_Logic_Vector(0 to 15));
END dek_4_16e;

ARCHITECTURE arhitektura OF dek_4_16e IS
  SIGNAL i_1 : Std_Logic_Vector(0 to 1); -- interni signali u prvom nivou
  SIGNAL i_2 : Std_Logic_Vector(0 to 3); -- interni signali u drugom nivou
  SIGNAL i_3 : Std_Logic_Vector(0 to 7); -- interni signali u trecem nivou

BEGIN
  sklop_1_0: ENTITY work.dek12e PORT MAP ( e, A(3), i_1(0), i_1(1) );

  sklop_2_0: ENTITY work.dek12e PORT MAP ( i_1(0), A(2), i_2(0), i_2(1) );
  sklop_2_1: ENTITY work.dek12e PORT MAP ( i_1(1), A(2), i_2(2), i_2(3) );

  sklop_3_0: ENTITY work.dek12e PORT MAP ( i_2(0), A(1), i_3(0), i_3(1) );
  sklop_3_1: ENTITY work.dek12e PORT MAP ( i_2(1), A(1), i_3(2), i_3(3) );
  sklop_3_2: ENTITY work.dek12e PORT MAP ( i_2(2), A(1), i_3(4), i_3(5) );
  sklop_3_3: ENTITY work.dek12e PORT MAP ( i_2(3), A(1), i_3(6), i_3(7) );

  sklop_4_0: ENTITY work.dek12e PORT MAP ( i_3(0), A(0), Y(0), Y(1) );
  sklop_4_1: ENTITY work.dek12e PORT MAP ( i_3(1), A(0), Y(2), Y(3) );
  sklop_4_2: ENTITY work.dek12e PORT MAP ( i_3(2), A(0), Y(4), Y(5) );
  sklop_4_3: ENTITY work.dek12e PORT MAP ( i_3(3), A(0), Y(6), Y(7) );
  sklop_4_4: ENTITY work.dek12e PORT MAP ( i_3(4), A(0), Y(8), Y(9) );
  sklop_4_5: ENTITY work.dek12e PORT MAP ( i_3(5), A(0), Y(10), Y(11) );
  sklop_4_6: ENTITY work.dek12e PORT MAP ( i_3(6), A(0), Y(12), Y(13) );
  sklop_4_7: ENTITY work.dek12e PORT MAP ( i_3(7), A(0), Y(14), Y(15) );
END arhitektura;