LIBRARY ieee;
use ieee.std_logic_1164.all;

ENTITY LAB_7_clocks IS
	PORT ( );
END ENTITY;

ARCHITECTURE Teller OF LAB_7_clocks IS

BEGIN

eight_bit: counter GENERIC MAP ( n =>8 )PORT MAP eight_bit (clock, reset_n, Q);


END Teller;


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY counter IS
GENERIC (   n : NATURAL := 8;
			K : NATURAL := 20);

PORT (  clock	: IN STD_LOGIC;
		reset_n	: IN STD_LOGIC;
		Q		: OUT STD_LOGIC_VECTOR(n−1 DOWNTO 0);
		rollover: OUT std_LOGIC);

END ENTITY;

ARCHITECTURE Behavior OF counter IS
SIGNAL value : STD_LOGIC_VECTOR(n−1 DOWNTO 0));
BEGIN
PROCESS (clock, reset_n)
BEGIN
IF (reset_n = ’0’)THEN
value<= (OTHERS => ’0’);
ELSIF ((clock’EVENT) AND (clock = 1 )) THEN
	IF (value > k) THEN
	value <=(OTHERS => ’0’);
	rollover <= 1;
	else
	value <= value + 1;
	end if;
END IF;
END PROCESS;
Q<= value;
END Behavior;