module ram128x16(
  input [6:0] adrs,
  inout [15:0] data,
  input _ce, _we, _oe

);
    reg [3:0] _cee;

  ram64x8 u1(adrs[5:0], data[15:8], _cee[0], _we, _oe);
  ram64x8 u2(adrs[5:0], data[7:0], _cee[0], _we, _oe);
  ram64x8 u3(adrs[5:0], data[15:8], _cee[1], _we, _oe);
  ram64x8 u4(adrs[5:0], data[7:0], _cee[1], _we, _oe);
  //1 - to - 2 decode
  always @ (*)
begin
    if(_ce == 0)
      case(adrs[6:6])
    0: _cee = 4'b1110;
    1: _cee = 4'b0111;
    default: _cee = 4'hf;
    endcase
    else
        _cee = 4'hf;
end
  endmodule