`timescale 1ns/1ps

module decide_max (result, valid, state, maximum, o_maximum);
    input [7:0] result;
    input valid;
    input [1:0] state;
    input [7:0] maximum;
    output [7:0] o_maximum;
    reg [7:0] o_maximum;

    always @(*) begin
        if (state != 0) begin
            if (valid && (result > maximum)) begin
                o_maximum = result;
            end
            else o_maximum = maximum;
        end
        else if (state == 0) begin
            o_maximum = 8'b00000000;
        end
    end
endmodule

module FSM (start, one_left, clk, rst_n, valid, state, o_finish);
    input start,one_left,valid,clk,rst_n;
    output [1:0] state;
    output o_finish;
    reg [1:0]state = 0;
    reg o_finish = 0;
    reg delay;

    always @(posedge clk) begin
        if (state == 0) begin
            o_finish = 0;
            if (start)
                state = 1;
        end
        if (state == 1 && !one_left) begin
            o_finish = 0;
        end
        else if (state == 1 && one_left) begin
            state = 2;
            o_finish = 0;
        end
        else if (delay) begin
            delay = 0;
            state = 0;
        end
        else if (state == 2 && !valid) begin
            o_finish = 0;
        end
        else if (state == 2 && valid) begin
            delay = 1;
            o_finish = 1;
        end
    end
endmodule

module Output_FFs (o_finish, clk, rst_n, o_maximum, maximum, finish);
    input [7:0] o_maximum;
    input o_finish;
    input clk;
    input rst_n;
    output [7:0] maximum;
    output finish;
    reg [7:0] maximum;
    reg finish;


    always @( posedge clk ) begin
        if (!rst_n)
            maximum = 8'b00000000;
        else begin
            maximum = o_maximum;
        end
        if (o_finish)
            finish = 1;
        else
            finish = 0;

    end

endmodule

module find_MAX(
    input wire clk,
    input wire rst_n,
    input wire start,
    input wire valid,
    input wire [7:0] Data_A,
    input wire [7:0] Data_B,
    input wire one_left,
    input wire [2:0] instruction,
    output reg [7:0] maximum,
    output reg finish
);
    wire [7:0] result;

    // Functional_Unit instantiation
    Functional_Unit fu(
        .instruction(instruction),
        .A(Data_A),
        .B(Data_B),
        .F(result)

    );

    //TODO: write your design below
    //You cannot modify anything above

    wire [1:0] state;
    wire o_finish;
    wire [7:0] Wmaximum;
    wire [7:0] o_maximum;
    wire wfinish;

    FSM fsm (start, one_left, clk, rst_n, valid, state, o_finish);
    Output_FFs off (o_finish, clk, rst_n, o_maximum, Wmaximum, wfinish);
    decide_max dmax (result, valid, state, Wmaximum, o_maximum);
    always @(*) begin
        maximum = Wmaximum;
        finish = wfinish;
    end

endmodule