Sreg.sv

module Sreg(
        input logic d,
        input logic c,
        output logic [7:0] q
    );

always @(posedge c) begin
    q[0] <= d;
    q[1] <= q[0];
    q[2] <= q[1];
    q[3] <= q[2];
    q[4] <= q[3];
    q[5] <= q[4];
    q[6] <= q[5];
    q[7] <= q[6];
end

endmodule