Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- ' Gambas module file
- ' The module was written by vuott from http://www.gambas-it.org/
- ' http://www.gambas-it.org/smf/index.php?action=profile;u=402
- Library "libcpuid"
- Property Read HT As String[]
- Property Read VIRTUALIZATION As String[]
- Property Read BITEXTENSIONS As String[]
- Property Read VERSION_CPUID_LIB As String
- Private LIBCPUID_VERSION As String
- Public Enum CPU_HINT_SSE_SIZE_AUTH = 0, NUM_CPU_HINTS
- Public Enum ARCHITECTURE_X86 = 0, ''/*!< x86 CPU */
- ARCHITECTURE_ARM, ''/*!< ARM CPU */
- NUM_CPU_ARCHITECTURES,''/*!< Valid CPU architecture ids: 0..NUM_CPU_ARCHITECTURES - 1 */
- ARCHITECTURE_UNKNOWN = -1
- Public Struct cpu_sgx_t
- present As Integer
- max_enclave_32bit As Byte
- max_enclave_64bit As Byte
- flags[14] As Byte
- num_epc_sections As Integer
- misc_select As Integer
- secs_attributes As Long
- secs_xfrm As Long
- End Struct
- Public Struct cpu_id_t
- '/** contains the CPU architecture ID(e.g.ARCHITECTURE_X86) * /
- ' cpu_architecture_t architecture;
- ''architecture As Integer ' 0 - 3
- vendor_str[16] As Byte ' 4 - 19
- brand_str[64] As Byte ' 20 - 83
- vendor As Integer ' 84 - 87
- flags[128] As Byte ' 88 - 215
- family As Integer ' 216 - 219
- model As Integer ' 220 - 223
- stepping As Integer ' 224 - 227
- ext_family As Integer ' 228 - 231
- ext_model As Integer ' 232 - 235
- num_cores As Integer ' 236 - 239
- num_logical_cpus As Integer ' 240 - 243
- total_logical_cpus As Integer ' 244 - 247
- l1_data_cache As Integer ' 248 - 251
- l1_instruction_cache As Integer ' 252 - 255
- l2_cache As Integer ' 256 - 259
- l3_cache As Integer ' 260 - 263
- l4_cache As Integer ' 264 - 267
- l1_assoc As Integer ' 268 - 271
- l1_data_assoc As Integer ' 272 - 275
- l1_instruction_assoc As Integer ' 276 - 279
- l2_assoc As Integer ' 280 - 283
- l3_assoc As Integer ' 284 - 287
- l4_assoc As Integer ' 288 - 291
- l1_cacheline As Integer ' 292 - 295
- l1_data_cacheline As Integer ' 296 - 299
- l1_instruction_cacheline As Integer ' 300 - 303
- l2_cacheline As Integer ' 304 - 307
- l3_cacheline As Integer ' 308 - 311
- l4_cacheline As Integer ' 312 - 315
- l1_data_instances As Integer ' 316 - 319
- l1_instruction_instances As Integer ' 320 - 323
- l2_instances As Integer ' 324 - 327
- l3_instances As Integer ' 328 - 331
- l4_instances As Integer ' 332 - 335
- cpu_codename[64] As Byte ' 336 - 399
- sse_size As Integer ' 400 - 403
- detection_hints[16] As Byte ' 404 - 419
- sgx As Struct Cpu_sgx_t ' 420 - 468
- End Struct
- Public Enum CPU_FEATURE_FPU = 0, '' Floating point unit */
- CPU_FEATURE_VME, '' Virtual mode extension */
- CPU_FEATURE_DE, '' Debugging extension */
- CPU_FEATURE_PSE, '' Page size extension */
- CPU_FEATURE_TSC, '' Time-stamp counter */
- CPU_FEATURE_MSR, '' Model-specific regsisters, RDMSR/WRMSR supported */
- CPU_FEATURE_PAE, '' Physical address extension */
- CPU_FEATURE_MCE, '' Machine check exception */
- CPU_FEATURE_CX8, '' CMPXCHG8B instruction supported */
- CPU_FEATURE_APIC, '' APIC support */
- CPU_FEATURE_MTRR, '' Memory type range registers */
- CPU_FEATURE_SEP, '' SYSENTER / SYSEXIT instructions supported */
- CPU_FEATURE_PGE, '' Page global enable */
- CPU_FEATURE_MCA, '' Machine check architecture */
- CPU_FEATURE_CMOV, '' CMOVxx instructions supported */
- CPU_FEATURE_PAT, '' Page attribute table */
- CPU_FEATURE_PSE36, '' 36-bit page address extension */
- CPU_FEATURE_PN, '' Processor serial # implemented (Intel P3 only) */
- CPU_FEATURE_CLFLUSH, '' CLFLUSH instruction supported */
- CPU_FEATURE_DTS, '' Debug store supported */
- CPU_FEATURE_ACPI, '' ACPI support (power states) */
- CPU_FEATURE_MMX, '' MMX instruction set supported */
- CPU_FEATURE_FXSR, '' FXSAVE / FXRSTOR supported */
- CPU_FEATURE_SSE, '' Streaming-SIMD Extensions (SSE) supported */
- CPU_FEATURE_SSE2, '' SSE2 instructions supported */
- CPU_FEATURE_SS, '' Self-snoop */
- CPU_FEATURE_HT, '' Hyper-threading supported (but might be disabled) */
- CPU_FEATURE_TM, '' Thermal monitor */
- CPU_FEATURE_IA64, '' IA64 supported (Itanium only) */
- CPU_FEATURE_PBE, '' Pending-break enable */
- CPU_FEATURE_PNI, '' PNI (SSE3) instructions supported */
- CPU_FEATURE_PCLMUL, '' PCLMULQDQ instruction supported */
- CPU_FEATURE_DTS64, '' 64-bit Debug store supported */
- CPU_FEATURE_MONITOR, '' MONITOR / MWAIT supported */
- CPU_FEATURE_DS_CPL, '' CPL Qualified Debug Store */
- CPU_FEATURE_VMX, '' Virtualization technology supported */
- CPU_FEATURE_SMX, '' Safer mode exceptions */
- CPU_FEATURE_EST, '' Enhanced SpeedStep */
- CPU_FEATURE_TM2, '' Thermal monitor 2 */
- CPU_FEATURE_SSSE3, '' SSSE3 instructionss supported (this is different from SSE3!) */
- CPU_FEATURE_CID, '' Context ID supported */
- CPU_FEATURE_CX16, '' CMPXCHG16B instruction supported */
- CPU_FEATURE_XTPR, '' Send Task Priority Messages disable */
- CPU_FEATURE_PDCM, '' Performance capabilities MSR supported */
- CPU_FEATURE_DCA, '' Direct cache access supported */
- CPU_FEATURE_SSE4_1, '' SSE 4.1 instructions supported */
- CPU_FEATURE_SSE4_2, '' SSE 4.2 instructions supported */
- CPU_FEATURE_SYSCALL, '' SYSCALL / SYSRET instructions supported */
- CPU_FEATURE_XD, '' Execute disable bit supported */
- CPU_FEATURE_MOVBE, '' MOVBE instruction supported */
- CPU_FEATURE_POPCNT, '' POPCNT instruction supported */
- CPU_FEATURE_AES, '' AES* instructions supported */
- CPU_FEATURE_XSAVE, '' XSAVE/XRSTOR/etc instructions supported */
- CPU_FEATURE_OSXSAVE, '' non-privileged copy of OSXSAVE supported */
- CPU_FEATURE_AVX, '' Advanced vector extensions supported */
- CPU_FEATURE_MMXEXT, '' AMD MMX-extended instructions supported */
- CPU_FEATURE_3DNOW, '' AMD 3DNow! instructions supported */
- CPU_FEATURE_3DNOWEXT, '' AMD 3DNow! extended instructions supported */
- CPU_FEATURE_NX, '' No-execute bit supported */
- CPU_FEATURE_FXSR_OPT, '' FFXSR: FXSAVE and FXRSTOR optimizations */
- CPU_FEATURE_RDTSCP, '' RDTSCP instruction supported (AMD-only) */
- CPU_FEATURE_LM, '' Long mode (x86_64/EM64T) supported */
- CPU_FEATURE_LAHF_LM, '' LAHF/SAHF supported in 64-bit mode */
- CPU_FEATURE_CMP_LEGACY, '' core multi-processing legacy mode */
- CPU_FEATURE_SVM, '' AMD Secure virtual machine */
- CPU_FEATURE_ABM, '' LZCNT instruction support */
- CPU_FEATURE_MISALIGNSSE, '' Misaligned SSE supported */
- CPU_FEATURE_SSE4A, '' SSE 4a from AMD */
- CPU_FEATURE_3DNOWPREFETCH, '' PREFETCH/PREFETCHW support */
- CPU_FEATURE_OSVW, '' OS Visible Workaround (AMD) */
- CPU_FEATURE_IBS, '' Instruction-based sampling */
- CPU_FEATURE_SSE5, '' SSE 5 instructions supported (deprecated, will never be 1) */
- CPU_FEATURE_SKINIT, '' SKINIT / STGI supported */
- CPU_FEATURE_WDT, '' Watchdog timer support */
- CPU_FEATURE_TS, '' Temperature sensor */
- CPU_FEATURE_FID, '' Frequency ID control */
- CPU_FEATURE_VID, '' Voltage ID control */
- CPU_FEATURE_TTP, '' THERMTRIP */
- CPU_FEATURE_TM_AMD, '' AMD-specified hardware thermal control */
- CPU_FEATURE_STC, '' Software thermal control */
- CPU_FEATURE_100MHZSTEPS, '' 100 MHz multiplier control */
- CPU_FEATURE_HWPSTATE, '' Hardware P-state control */
- CPU_FEATURE_CONSTANT_TSC, '' TSC ticks at constant rate */
- CPU_FEATURE_XOP, '' The XOP instruction set (same as the old CPU_FEATURE_SSE5) */
- CPU_FEATURE_FMA3, '' The FMA3 instruction set */
- CPU_FEATURE_FMA4, '' The FMA4 instruction set */
- CPU_FEATURE_TBM, '' Trailing bit manipulation instruction support */
- CPU_FEATURE_F16C, '' 16-bit FP convert instruction support */
- CPU_FEATURE_RDRAND, '' RdRand instruction */
- CPU_FEATURE_X2APIC, '' x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) also see standard level 0000_000Bh */
- CPU_FEATURE_CPB, '' Core performance boost */
- CPU_FEATURE_APERFMPERF, '' MPERF/APERF MSRs support */
- CPU_FEATURE_PFI, '' Processor Feedback Interface support */
- CPU_FEATURE_PA, '' Processor accumulator */
- CPU_FEATURE_AVX2, '' AVX2 instructions */
- CPU_FEATURE_BMI1, '' BMI1 instructions */
- CPU_FEATURE_BMI2, '' BMI2 instructions */
- CPU_FEATURE_HLE, '' Hardware Lock Elision prefixes */
- CPU_FEATURE_RTM, '' Restricted Transactional Memory instructions */
- CPU_FEATURE_AVX512F, '' AVX-512 Foundation */
- CPU_FEATURE_AVX512DQ, '' AVX-512 Double/Quad granular insns */
- CPU_FEATURE_AVX512PF, '' AVX-512 Prefetch */
- CPU_FEATURE_AVX512ER, '' AVX-512 Exponential/Reciprocal */
- CPU_FEATURE_AVX512CD, '' AVX-512 Conflict detection */
- CPU_FEATURE_SHA_NI, '' SHA-1/SHA-256 instructions */
- CPU_FEATURE_AVX512BW, '' AVX-512 Byte/Word granular insns */
- CPU_FEATURE_AVX512VL, '' AVX-512 128/256 vector length extensions */
- CPU_FEATURE_SGX, '' SGX extensions. Non-autoritative, check cpu_id_t::sgx::present to verify presence */
- CPU_FEATURE_RDSEED, '' RDSEED instruction */
- CPU_FEATURE_ADX, '' ADX extensions (arbitrary precision) */
- CPU_FEATURE_AVX512VNNI, '' AVX-512 Vector Neural Network Instructions */
- CPU_FEATURE_AVX512VBMI, ''/*!< AVX-512 Vector Bit ManipulationInstructions (version 1) */
- CPU_FEATURE_AVX512VBMI2, ''/*!< AVX-512 Vector Bit ManipulationInstructions (version 2) */
- NUM_CPU_FEATURES
- ' Private CPU_FEATURE_STRING As String[][] = [
- ' [CPU_FEATURE_FPU, "fpu"],
- ' [CPU_FEATURE_VME, "vme"],
- ' [CPU_FEATURE_DE, "de"],
- ' [CPU_FEATURE_PSE, "pse"],
- ' [CPU_FEATURE_TSC, "tsc"],
- ' [CPU_FEATURE_MSR, "msr"],
- ' [CPU_FEATURE_PAE, "pae"],
- ' [CPU_FEATURE_MCE, "mce"],
- ' [CPU_FEATURE_CX8, "cx8"],
- ' [CPU_FEATURE_APIC, "apic"],
- ' [CPU_FEATURE_MTRR, "mtrr"],
- ' [CPU_FEATURE_SEP, "sep"],
- ' [CPU_FEATURE_PGE, "pge"],
- ' [CPU_FEATURE_MCA, "mca"],
- ' [CPU_FEATURE_CMOV, "cmov"],
- ' [CPU_FEATURE_PAT, "pat"],
- ' [CPU_FEATURE_PSE36, "pse36"],
- ' [CPU_FEATURE_PN, "pn"],
- ' [CPU_FEATURE_CLFLUSH, "clflush"],
- ' [CPU_FEATURE_DTS, "dts"],
- ' [CPU_FEATURE_ACPI, "acpi"],
- ' [CPU_FEATURE_MMX, "mmx"],
- ' [CPU_FEATURE_FXSR, "fxsr"],
- ' [CPU_FEATURE_SSE, "sse"],
- ' [CPU_FEATURE_SSE2, "sse2"],
- ' [CPU_FEATURE_SS, "ss"],
- ' [CPU_FEATURE_HT, "ht"],
- ' [CPU_FEATURE_TM, "tm"],
- ' [CPU_FEATURE_IA64, "ia64"],
- ' [CPU_FEATURE_PBE, "pbe"],
- ' [CPU_FEATURE_PNI, "pni"],
- ' [CPU_FEATURE_PCLMUL, "pclmul"],
- ' [CPU_FEATURE_DTS64, "dts64"],
- ' [CPU_FEATURE_MONITOR, "monitor"],
- ' [CPU_FEATURE_DS_CPL, "ds_cpl"],
- ' [CPU_FEATURE_VMX, "vmx"],
- ' [CPU_FEATURE_SMX, "smx"],
- ' [CPU_FEATURE_EST, "est"],
- ' [CPU_FEATURE_TM2, "tm2"],
- ' [CPU_FEATURE_SSSE3, "ssse3"],
- ' [CPU_FEATURE_CID, "cid"],
- ' [CPU_FEATURE_CX16, "cx16"],
- ' [CPU_FEATURE_XTPR, "xtpr"],
- ' [CPU_FEATURE_PDCM, "pdcm"],
- ' [CPU_FEATURE_DCA, "dca"],
- ' [CPU_FEATURE_SSE4_1, "sse4_1"],
- ' [CPU_FEATURE_SSE4_2, "sse4_2"],
- ' [CPU_FEATURE_SYSCALL, "syscall"],
- ' [CPU_FEATURE_XD, "xd"],
- ' [CPU_FEATURE_X2APIC, "x2apic"],
- ' [CPU_FEATURE_MOVBE, "movbe"],
- ' [CPU_FEATURE_POPCNT, "popcnt"],
- ' [CPU_FEATURE_AES, "aes"],
- ' [CPU_FEATURE_XSAVE, "xsave"],
- ' [CPU_FEATURE_OSXSAVE, "osxsave"],
- ' [CPU_FEATURE_AVX, "avx"],
- ' [CPU_FEATURE_MMXEXT, "mmxext"],
- ' [CPU_FEATURE_3DNOW, "3dnow"],
- ' [CPU_FEATURE_3DNOWEXT, "3dnowext"],
- ' [CPU_FEATURE_NX, "nx"],
- ' [CPU_FEATURE_FXSR_OPT, "fxsr_opt"],
- ' [CPU_FEATURE_RDTSCP, "rdtscp"],
- ' [CPU_FEATURE_LM, "lm"],
- ' [CPU_FEATURE_LAHF_LM, "lahf_lm"],
- ' [CPU_FEATURE_CMP_LEGACY, "cmp_legacy"],
- ' [CPU_FEATURE_SVM, "svm"],
- ' [CPU_FEATURE_SSE4A, "sse4a"],
- ' [CPU_FEATURE_MISALIGNSSE, "misalignsse"],
- ' [CPU_FEATURE_ABM, "abm"],
- ' [CPU_FEATURE_3DNOWPREFETCH, "3dnowprefetch"],
- ' [CPU_FEATURE_OSVW, "osvw"],
- ' [CPU_FEATURE_IBS, "ibs"],
- ' [CPU_FEATURE_SSE5, "sse5"],
- ' [CPU_FEATURE_SKINIT, "skinit"],
- ' [CPU_FEATURE_WDT, "wdt"],
- ' [CPU_FEATURE_TS, "ts"],
- ' [CPU_FEATURE_FID, "fid"],
- ' [CPU_FEATURE_VID, "vid"],
- ' [CPU_FEATURE_TTP, "ttp"],
- ' [CPU_FEATURE_TM_AMD, "tm_amd"],
- ' [CPU_FEATURE_STC, "stc"],
- ' [CPU_FEATURE_100MHZSTEPS, "100mhzsteps"],
- ' [CPU_FEATURE_HWPSTATE, "hwpstate"],
- ' [CPU_FEATURE_CONSTANT_TSC, "constant_tsc"],
- ' [CPU_FEATURE_XOP, "xop"],
- ' [CPU_FEATURE_FMA3, "fma3"],
- ' [CPU_FEATURE_FMA4, "fma4"],
- ' [CPU_FEATURE_TBM, "tbm"],
- ' [CPU_FEATURE_F16C, "f16c"],
- ' [CPU_FEATURE_RDRAND, "rdrand"],
- ' [CPU_FEATURE_CPB, "cpb"],
- ' [CPU_FEATURE_APERFMPERF, "aperfmperf"],
- ' [CPU_FEATURE_PFI, "pfi"],
- ' [CPU_FEATURE_PA, "pa"],
- ' [CPU_FEATURE_AVX2, "avx2"],
- ' [CPU_FEATURE_BMI1, "bmi1"],
- ' [CPU_FEATURE_BMI2, "bmi2"],
- ' [CPU_FEATURE_HLE, "hle"],
- ' [CPU_FEATURE_RTM, "rtm"],
- ' [CPU_FEATURE_AVX512F, "avx512f"],
- ' [CPU_FEATURE_AVX512DQ, "avx512dq"],
- ' [CPU_FEATURE_AVX512PF, "avx512pf"],
- ' [CPU_FEATURE_AVX512ER, "avx512er"],
- ' [CPU_FEATURE_AVX512CD, "avx512cd"],
- ' [CPU_FEATURE_SHA_NI, "sha_ni"],
- ' [CPU_FEATURE_AVX512BW, "avx512bw"],
- ' [CPU_FEATURE_AVX512VL, "avx512vl"],
- ' [CPU_FEATURE_SGX, "sgx"],
- ' [CPU_FEATURE_RDSEED, "rdseed"],
- ' [CPU_FEATURE_ADX, "adx"],
- ' [CPU_FEATURE_AVX512VNNI, "avx512vnni"],
- ' [CPU_FEATURE_AVX512VBMI, "avx512vbmi"],
- ' [CPU_FEATURE_AVX512VBMI2, "avx512vbmi2"]
- ' ]
- Private CPU_FLAGS_SHORT As String[][] = [
- [CPU_FEATURE_MMX, "MMX"],
- [CPU_FEATURE_MMXEXT, "(+)"],
- [CPU_FEATURE_3DNOW, "3DNOW!"],
- [CPU_FEATURE_3DNOWEXT, "(+)"],
- [CPU_FEATURE_SSE, "SSE(1"],
- [CPU_FEATURE_SSE2, "2"],
- [CPU_FEATURE_PNI, "3"],
- [CPU_FEATURE_SSSE3, "3S"],
- [CPU_FEATURE_SSE4_1, "4.1"],
- [CPU_FEATURE_SSE4_2, "4.2"],
- [CPU_FEATURE_SSE4A, "4A"],
- [CPU_FEATURE_SSE, ")"],
- [CPU_FEATURE_XOP, "XOP"],
- [CPU_FEATURE_AVX, "AVX(1"],
- [CPU_FEATURE_AVX2, "2"],
- [CPU_FEATURE_AVX512F, "512"],
- [CPU_FEATURE_AVX, ")"],
- [CPU_FEATURE_FMA3, "FMA(3"],
- [CPU_FEATURE_FMA4, "4"],
- [CPU_FEATURE_FMA3, ")"],
- [CPU_FEATURE_AES, "AES"],
- [CPU_FEATURE_PCLMUL, "CLMUL"],
- [CPU_FEATURE_RDRAND, "RdRand"],
- [CPU_FEATURE_SHA_NI, "SHA"],
- [CPU_FEATURE_SGX, "SGX"],
- [CPU_FEATURE_VMX, "VT-x"],
- [CPU_FEATURE_SVM, "AMD-V"],
- [CPU_FEATURE_LM, "x86-64"]
- ]
- Public Enum VENDOR_INTEL = 0, ''/*!< Intel CPU */
- VENDOR_AMD, ''/*!< AMD CPU */
- VENDOR_CYRIX, ''/*!< Cyrix CPU */
- VENDOR_NEXGEN, ''/*!< NexGen CPU */
- VENDOR_TRANSMETA, ''/*!< Transmeta CPU */
- VENDOR_UMC, ''/*!< x86 CPU by UMC */
- VENDOR_CENTAUR, ''/*!< x86 CPU by IDT */
- VENDOR_RISE, ''/*!< x86 CPU by Rise Technology */
- VENDOR_SIS, ''/*!< x86 CPU by SiS */
- VENDOR_NSC, ''/*!< x86 CPU by National Semiconductor */
- VENDOR_HYGON, ''/*!< Hygon CPU */
- NUM_CPU_VENDORS, ''/*!< Valid CPU vendor ids: 0..NUM_CPU_VENDORS - 1 */
- VENDOR_UNKNOWN = -1
- Public Enum INTEL_SGX1, ''/*!< SGX1 instructions support */
- INTEL_SGX2, ''/*!< SGX2 instructions support */
- NUM_SGX_FEATURES
- Private cpu_vendor_string As String[] = ["GenuineIntel",
- "AuthenticAMD",
- "CyrixInstead",
- "NexGenDriven",
- "GenuineTMx86",
- "UMC UMC UMC ",
- "CentaurHauls",
- "RiseRiseRise",
- "SiS SiS SiS ",
- "Geode by NSC",
- "HygonGenuine"]
- Public manufacturer_name As String[] = ["Intel",
- "AMD",
- "Cyrix",
- "NexGen",
- "Transmeta",
- "UMC",
- "Centaur",
- "Rise",
- "SiS",
- "Geode",
- "Hygon"]
- Public Struct cpu_list_t
- num_entries As Integer
- names[200] As Pointer
- End Struct
- Public Struct cpu_raw_data_t
- basic_cpuid[32, 4] As Integer
- ext_cpuid[32, 4] As Integer
- intel_fn4[8, 4] As Integer
- intel_fn11[4, 4] As Integer
- intel_fn12h[4, 4] As Integer
- intel_fn14h[4, 4] As Integer
- amd_fn8000001dh[4, 4] As Integer
- End Struct
- Public Struct cpu_mark_t
- tsc As Long
- sys_clock As Long
- End Struct
- Public Struct cpu_epc_t
- start_addr As Long
- length As Long
- End Struct
- Private Extern cpuid_present() As Integer
- Private Extern cpuid_lib_version() As String
- Private Extern get_total_cpus() As Integer
- Private Extern cpuid_get_raw_data(raw As Cpu_raw_data_t) As Integer
- ''int cpuid_serialize_raw_data(struct cpu_raw_data_t* data, const char* filename);
- ''int cpuid_deserialize_raw_data(struct cpu_raw_data_t* data, const char* filename);
- Private Extern cpuid_error() As String
- Private Extern cpu_identify(raw As Cpu_raw_data_t, data As Cpu_id_t) As Integer
- ' /**
- ' * @brief Returns the short textual representation of a CPU architecture
- ' * @param architecture - the architecture, whose textual representation is wanted.
- ' * @returns a constant string like "x86", "ARM", etc.
- ' */
- ' const char* cpu_architecture_str(cpu_architecture_t architecture);
- ''Public Extern cpu_architecture_str(architecture As Integer) As String
- Public Extern cpu_tsc_mark(mark As Cpu_mark_t)
- Public Extern cpu_tsc_unmark(mark As Cpu_mark_t)
- ''int cpu_clock_by_mark(struct cpu_mark_t * mark);
- Public Extern cpu_clock_by_mark(mark As Cpu_mark_t)
- Public Extern cpu_clock() As Integer
- Public Extern cpu_clock_by_os() As Integer
- Public Extern cpu_clock_by_ic(millis As Integer, runs As Integer) As Integer
- Public Extern cpu_clock_measure(millis As Integer, quad_check As Integer) As Integer
- Public Extern cpu_feature_str(feature As Integer) As String
- Private Extern cpuid_get_cpu_list(vendor As Integer, cpu_list As Cpu_list_t) As Integer
- Private Extern cpuid_free_cpu_list(cpu_list As Cpu_list_t)
- 'void cpuid_get_cpu_list(cpu_vendor_t vendor, struct cpu_list_t* list)
- Public mark As New Cpu_mark_t
- Public data As New Cpu_id_t
- Public data_flags As Pointer
- Property Read cpuflags_short As String
- Private Function cpuflags_short_Read() As String
- Dim short_flags As String
- Dim i, z As Integer
- For z = 0 To CPU_FLAGS_SHORT.Max
- For i = 0 To NUM_CPU_FEATURES - 1
- If Byte@(data_flags + (i + 84)) > 0 Then
- If CPU_FLAGS_SHORT[z][0] = i Then
- short_flags &= CPU_FLAGS_SHORT[z][1] & " "
- Endif
- Endif
- Next
- Next
- clean()
- Return short_flags
- End
- Public Sub _init()
- Dim raw As New Cpu_raw_data_t
- ''Dim mark As New Cpu_mark_t
- Dim datas As New Cpu_list_t
- Dim au As String
- Dim fl As File
- If Not cpuid_present() Then Error.Raise("Sorry, your CPU doesn't support CPUID !")
- If cpuid_get_raw_data(raw) < 0 Then
- Error.Raise("Sorry, cannot get the CPUID raw data.\nError: " & cpuid_error())
- Endif
- data = Alloc(SizeOf(gb.Byte), 512)
- data_flags = Alloc(SizeOf(gb.Byte), 512)
- If cpu_identify(raw, data) < 0 And cpu_identify(raw, data_flags) < 0 Then
- Error.Raise("Sorry, CPU identification failed.\nError: " & cpuid_error())
- Endif
- ''cpu_tsc_mark(mark)
- ''Wait 0.10
- ''cpu_tsc_unmark(mark)
- ''cpu_clock_by_mark(mark)
- ' If (data.sgx.present) Then
- ' Print Subst("SGX max enclave size (32-bit): &1", data.sgx.max_enclave_32bit)
- ' Print Subst("SGX max enclave size (64-bit): &1", data.sgx.max_enclave_64bit)
- ' Print Subst("SGX1 extensions : &1 &2", data.sgx.flags[INTEL_SGX1], IIf(data.sgx.flags[INTEL_SGX1], "present", "absent"))
- ' Print Subst("SGX2 extensions : &1 &2", data.sgx.flags[INTEL_SGX2], IIf(data.sgx.flags[INTEL_SGX2], "present", "absent"))
- ' Print Subst("SGX MISCSELECT : &1", data.sgx.misc_select)
- ' Print Subst("SGX SECS.ATTRIBUTES mask : &1", data.sgx.secs_attributes)
- ' Print Subst("SGX SECS.XSAVE feature mask : &1", data.sgx.secs_xfrm)
- ' Print Subst("SGX EPC sections count : &1", data.sgx.num_epc_sections)
- ' Endif
- Try LIBCPUID_VERSION = cpuid_lib_version()
- If Error Then LIBCPUID_VERSION = "<Unknown>"
- ' Print ""; IIf(gb.BigEndian, "BigEndian", "LittleEndian")
- ' Print ""; IIf(gb.LittleEndian, "LittleEndian", "BigEndian")
- Print "CPUID is "; IIf(cpuid_present(), "present", "absent")
- Print "CPU Info:"
- Print "------------------"
- Print " vendor_str : "; String@(data.vendor_str.Data) '' cpu_vendor_string[data.vendor]
- Print " manufaturer: "; manufacturer_name[data.vendor]
- Print " vendor id : "; (data.vendor)
- Print " brand_str : "; String@(data.brand_str.data)
- Print " family : "; data.family
- Print " model : "; data.model
- Print " stepping : "; data.stepping
- ' Print " ext_family : "; data.ext_family
- ' Print " ext_model : "; data.ext_model
- ' Print " num_cores : "; data.num_cores
- ' Print " num_logical: "; data.num_logical_cpus
- ' Print " tot_logical: "; data.total_logical_cpus
- '
- ' Print " L1 D cache : "; data.l1_data_cache; " KB"
- ' Print " L1 I cache : "; data.l1_instruction_cache; " KB"
- '
- ' Print " L2 cache : "; data.l2_cache; " KB"
- ' Print " L3 cache : "; data.l3_cache; " KB"
- ' Print " L4 cache : "; data.l4_cache; " KB"
- '
- ' Print " L1 assoc. : "; data.l1_assoc; "-way"
- ' Print " L1D assoc. : "; data.l1_data_assoc; "-way"
- ' Print " L1I assoc. : "; data.l1_instruction_assoc; "-way"
- '
- ' Print " L2 assoc. : "; data.l2_assoc; "-way"
- ' Print " L3 assoc. : "; data.l3_assoc; "-way"
- ' Print " L4 assoc. : "; data.l4_assoc; "-way"
- '
- ' Print " L1C line sz: "; data.l1_cacheline; " bytes"
- ' Print " L1D line sz: "; data.l1_data_cacheline; " bytes"
- ' Print " L1I line sz: "; data.l1_instruction_cacheline; " bytes"
- '
- ' Print " L2 line sz : "; data.l2_cacheline; " bytes"
- ' Print " L3 line sz : "; data.l3_cacheline; " bytes"
- ' Print " L4 line sz : "; data.l4_cacheline; " bytes"
- Print " SSE units : "; data.sse_size; " bit "; IIf(data.detection_hints[CPU_HINT_SSE_SIZE_AUTH], "(authoritative)", "(non-authoritative)")
- Print " code name : "; String@(data.cpu_codename.data)
- ' Print " Supported features : ";
- ' For i = 0 To NUM_CPU_FEATURES - 1
- ' If Byte@(data_flags + (i + 84)) > 0 Then
- ' For z = 0 To CPU_FLASGS_SHORT.Max
- ' If i = CPU_FLASGS_SHORT[z][0] Then
- ' Print CPU_FLASGS_SHORT[z][i]
- ' Endif
- ' Next
- ' If cpu_feature_str(CPU_FEATURE_SSE) = cpu_feature_str(i) Then
- ' Print " "; cpu_feature_str(i);
- ' Endif
- ' Endif
- ''Print " \"FEATURE\": "; cpu_feature_str(i); IIf(Byte@(data_flags + (i + 84)), " Present", " Absent");
- 'Next
- ' Print "\n"
- ' Print " Unsupported features : ";
- ' Dim i As Integer
- ' For i = 0 To NUM_CPU_FEATURES
- '
- ' If Byte@(data_flags + (i + 84)) = 1 Then
- ' Print " "; cpu_feature_str(i);
- ' Endif
- ' '
- ' ' Print " \"FEATURE\": "; cpu_feature_str(i); IIf(Byte@(data_flags + (i + 84)), " Present", " Absent");
- ' ' Print "\n"
- ' Next
- 'Free(data_flags)
- ' Print " \"CPU_CLOCK\": "; cpu_clock(); " Mhz"
- ' Print " \"CPU_CLOCK_BY_OS\": "; cpu_clock_by_os(); " Mhz"
- ' Print " \"CPU_CLOCK_BY_IC\": "; cpu_clock_by_ic(25, 16); " Mhz"
- ' Print " \"CPU_CLOCK_MEASURE\": "; cpu_clock_measure(400, 1); " Mhz"
- ' Print " \"MARK_TSC\": "; mark.tsc
- ' Print " \"MARK_SYS_CLOCK\": "; mark.sys_clock
- ' For i = 0 To 124
- ' If data.flags[i] >= &h1 Then
- ' Print cpu_feature_str(i); " ";
- ' Endif
- ' ''Print " \"FEATURE\": "; cpu_feature_str(i); IIf((data.flags[i] >= &h1), " Present", " Absent")
- ' Next
- 'For i = 0 To NUM_CPU_FEATURES - 1
- 'Print cpu_feature_str(CPU_FEATURE_LM) & " || " & IIf(Byte@(data_flags + (CPU_FEATURE_LM + 84)), " Present", " Absent")
- 'Next
- ' Print NUM_CPU_FEATURES
- ''Free(data_flags)
- ''Free(data)
- End
- Private Function HT_Read() As String[]
- Select Case Libcpuid.data.vendor
- Case VENDOR_INTEL
- If Byte@(data_flags + (CPU_FEATURE_HT + 84)) = 1 Then
- Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
- Else If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
- Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
- Else If Exist("/sys/devices/system/cpu/smt/") = True Then
- Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
- Else
- Return ["Hyper-Threading:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- Endif
- Case VENDOR_AMD
- If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
- Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
- Else If Exist("/sys/devices/system/cpu/smt/") = True Then
- Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
- Else
- Return ["Hyper-Transport:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- Endif
- End Select
- ' If Byte@(Libcpuid.data_flags + (Libcpuid.CPU_FEATURE_HT + 84)) = 1 Then
- ' If Libcpuid.data.vendor = Libcpuid.VENDOR_INTEL Then
- ' Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
- ' Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
- ' Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
- ' Endif
- ' Else If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
- ' If Libcpuid.data.vendor = Libcpuid.VENDOR_INTEL Then
- ' Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
- ' Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
- ' Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
- ' Endif
- ' Else If Libcpuid.data.vendor = VENDOR_INTEL Then
- ' Return ["Hyper-Threading:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- ' Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
- ' Return ["Hyper-Transport:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- ' Endif
- End
- Private Function VIRTUALIZATION_Read() As String[]
- If Byte@(data_flags + (CPU_FEATURE_VMX + 84)) Then
- Return ["Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
- Else If Byte@(data_flags + (CPU_FEATURE_SVM) + 84) Then
- Return ["HW Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
- Else If Exist("/dev/kvm") = True Then
- Return ["HW Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
- Else
- Return ["HW Virtualization", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- Endif
- End
- 'CPU_FEATURE_NX
- 'CPU_FEATURE_XD
- 'CPU_FEATURE_LM
- Private Function BITEXTENSIONS_Read() As String[]
- If Byte@((data_flags + (CPU_FEATURE_LM + 84))) Then
- Return ["X86-64 Bit Ext", True, ".public/48x48/emblems/emblem-default.svg"]
- Else
- Return ["X86-64 Bit Ext", False, ".public/48x48/emblems/emblem-unreadable.svg"]
- Endif
- End
- Public Sub clean()
- Free(data_flags)
- End
- Private Function VERSION_CPUID_LIB_Read() As String
- Return LIBCPUID_VERSION
- End
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement