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  1. ' Gambas module file
  2.  
  3. ' The module was written by vuott from http://www.gambas-it.org/
  4. ' http://www.gambas-it.org/smf/index.php?action=profile;u=402
  5.  
  6. Library "libcpuid"
  7.  
  8. Property Read HT As String[]
  9. Property Read VIRTUALIZATION As String[]
  10. Property Read BITEXTENSIONS As String[]
  11. Property Read VERSION_CPUID_LIB As String
  12.  
  13.  
  14. Private LIBCPUID_VERSION As String
  15.  
  16. Public Enum CPU_HINT_SSE_SIZE_AUTH = 0, NUM_CPU_HINTS
  17.  
  18. Public Enum ARCHITECTURE_X86 = 0, ''/*!< x86 CPU */
  19.             ARCHITECTURE_ARM,     ''/*!< ARM CPU */
  20.             NUM_CPU_ARCHITECTURES,''/*!< Valid CPU architecture ids: 0..NUM_CPU_ARCHITECTURES - 1 */
  21.             ARCHITECTURE_UNKNOWN = -1
  22.  
  23. Public Struct cpu_sgx_t
  24.   present As Integer
  25.   max_enclave_32bit As Byte
  26.   max_enclave_64bit As Byte
  27.   flags[14] As Byte
  28.   num_epc_sections As Integer
  29.   misc_select As Integer
  30.   secs_attributes As Long
  31.   secs_xfrm As Long
  32. End Struct
  33.  
  34. Public Struct cpu_id_t
  35.  '/** contains the CPU architecture ID(e.g.ARCHITECTURE_X86) * /
  36.  ' cpu_architecture_t architecture;
  37.   ''architecture As Integer         '  0 -  3
  38.   vendor_str[16] As Byte          '  4 -  19
  39.   brand_str[64] As Byte           '  20 -  83
  40.   vendor As Integer               '  84 -  87
  41.   flags[128] As Byte              '  88 - 215
  42.   family As Integer               '  216 - 219
  43.   model As Integer                '  220 - 223
  44.   stepping As Integer             '  224 - 227
  45.   ext_family As Integer           '  228 - 231
  46.   ext_model As Integer            '  232 - 235
  47.   num_cores As Integer            '  236 - 239
  48.   num_logical_cpus As Integer     '  240 - 243
  49.   total_logical_cpus As Integer   '  244 - 247
  50.   l1_data_cache As Integer        '  248 - 251
  51.   l1_instruction_cache As Integer '  252 - 255
  52.   l2_cache As Integer             '  256 - 259
  53.   l3_cache As Integer             '  260 - 263
  54.   l4_cache As Integer             '  264 - 267
  55.   l1_assoc As Integer             '  268 - 271
  56.   l1_data_assoc As Integer        '  272 - 275
  57.   l1_instruction_assoc As Integer '  276 - 279
  58.   l2_assoc As Integer             '  280 - 283
  59.   l3_assoc As Integer             '  284 - 287
  60.   l4_assoc As Integer             '  288 - 291
  61.   l1_cacheline As Integer         '  292 - 295
  62.   l1_data_cacheline As Integer    '  296 - 299
  63.   l1_instruction_cacheline As Integer '  300 - 303
  64.   l2_cacheline As Integer         '  304 - 307
  65.   l3_cacheline As Integer         '  308 - 311
  66.   l4_cacheline As Integer         '  312 - 315
  67.   l1_data_instances As Integer    '  316 - 319
  68.   l1_instruction_instances As Integer   '  320 - 323
  69.   l2_instances As Integer         '  324 - 327
  70.   l3_instances As Integer         '  328 - 331
  71.   l4_instances As Integer         '  332 - 335
  72.   cpu_codename[64] As Byte        '  336 - 399
  73.   sse_size As Integer             '  400 - 403
  74.   detection_hints[16] As Byte     '  404 - 419
  75.   sgx As Struct Cpu_sgx_t         '  420 - 468
  76. End Struct
  77.  
  78. Public Enum CPU_FEATURE_FPU = 0,  '' Floating point unit */
  79.  CPU_FEATURE_VME,  '' Virtual mode extension */
  80.  CPU_FEATURE_DE,   '' Debugging extension */
  81.  CPU_FEATURE_PSE,  '' Page size extension */
  82.  CPU_FEATURE_TSC,  '' Time-stamp counter */
  83.  CPU_FEATURE_MSR,  '' Model-specific regsisters, RDMSR/WRMSR supported */
  84.  CPU_FEATURE_PAE,  '' Physical address extension */
  85.  CPU_FEATURE_MCE,  '' Machine check exception */
  86.  CPU_FEATURE_CX8,  '' CMPXCHG8B instruction supported */
  87.  CPU_FEATURE_APIC,  '' APIC support */
  88.  CPU_FEATURE_MTRR,  '' Memory type range registers */
  89.  CPU_FEATURE_SEP,  '' SYSENTER / SYSEXIT instructions supported */
  90.  CPU_FEATURE_PGE,  '' Page global enable */
  91.  CPU_FEATURE_MCA,  '' Machine check architecture */
  92.  CPU_FEATURE_CMOV,  '' CMOVxx instructions supported */
  93.  CPU_FEATURE_PAT,  '' Page attribute table */
  94.  CPU_FEATURE_PSE36,  '' 36-bit page address extension */
  95.  CPU_FEATURE_PN,   '' Processor serial # implemented (Intel P3 only) */
  96.  CPU_FEATURE_CLFLUSH,  '' CLFLUSH instruction supported */
  97.  CPU_FEATURE_DTS,  '' Debug store supported */
  98.  CPU_FEATURE_ACPI,  '' ACPI support (power states) */
  99.  CPU_FEATURE_MMX,  '' MMX instruction set supported */
  100.  CPU_FEATURE_FXSR,  '' FXSAVE / FXRSTOR supported */
  101.  CPU_FEATURE_SSE,  '' Streaming-SIMD Extensions (SSE) supported */
  102.  CPU_FEATURE_SSE2,  '' SSE2 instructions supported */
  103.  CPU_FEATURE_SS,   '' Self-snoop */
  104.  CPU_FEATURE_HT,   '' Hyper-threading supported (but might be disabled) */
  105.  CPU_FEATURE_TM,   '' Thermal monitor */
  106.  CPU_FEATURE_IA64,  '' IA64 supported (Itanium only) */
  107.  CPU_FEATURE_PBE,  '' Pending-break enable */
  108.  CPU_FEATURE_PNI,  '' PNI (SSE3) instructions supported */
  109.  CPU_FEATURE_PCLMUL,  '' PCLMULQDQ instruction supported */
  110.  CPU_FEATURE_DTS64,  '' 64-bit Debug store supported */
  111.  CPU_FEATURE_MONITOR,  '' MONITOR / MWAIT supported */
  112.  CPU_FEATURE_DS_CPL,  '' CPL Qualified Debug Store */
  113.  CPU_FEATURE_VMX,  '' Virtualization technology supported */
  114.  CPU_FEATURE_SMX,  '' Safer mode exceptions */
  115.  CPU_FEATURE_EST,  '' Enhanced SpeedStep */
  116.  CPU_FEATURE_TM2,  '' Thermal monitor 2 */
  117.  CPU_FEATURE_SSSE3,  '' SSSE3 instructionss supported (this is different from SSE3!) */
  118.  CPU_FEATURE_CID,  '' Context ID supported */
  119.  CPU_FEATURE_CX16,  '' CMPXCHG16B instruction supported */
  120.  CPU_FEATURE_XTPR,  '' Send Task Priority Messages disable */
  121.  CPU_FEATURE_PDCM,  '' Performance capabilities MSR supported */
  122.  CPU_FEATURE_DCA,  '' Direct cache access supported */
  123.  CPU_FEATURE_SSE4_1,  '' SSE 4.1 instructions supported */
  124.  CPU_FEATURE_SSE4_2,  '' SSE 4.2 instructions supported */
  125.  CPU_FEATURE_SYSCALL,  '' SYSCALL / SYSRET instructions supported */
  126.  CPU_FEATURE_XD,   '' Execute disable bit supported */
  127.  CPU_FEATURE_MOVBE,  '' MOVBE instruction supported */
  128.  CPU_FEATURE_POPCNT,  '' POPCNT instruction supported */
  129.  CPU_FEATURE_AES,  '' AES* instructions supported */
  130.  CPU_FEATURE_XSAVE,  '' XSAVE/XRSTOR/etc instructions supported */
  131.  CPU_FEATURE_OSXSAVE,  '' non-privileged copy of OSXSAVE supported */
  132.  CPU_FEATURE_AVX,  '' Advanced vector extensions supported */
  133.  CPU_FEATURE_MMXEXT,  '' AMD MMX-extended instructions supported */
  134.  CPU_FEATURE_3DNOW,  '' AMD 3DNow! instructions supported */
  135.  CPU_FEATURE_3DNOWEXT,  '' AMD 3DNow! extended instructions supported */
  136.  CPU_FEATURE_NX,   '' No-execute bit supported */
  137.  CPU_FEATURE_FXSR_OPT,  '' FFXSR: FXSAVE and FXRSTOR optimizations */
  138.  CPU_FEATURE_RDTSCP,  '' RDTSCP instruction supported (AMD-only) */
  139.  CPU_FEATURE_LM,   '' Long mode (x86_64/EM64T) supported */
  140.  CPU_FEATURE_LAHF_LM,  '' LAHF/SAHF supported in 64-bit mode */
  141.  CPU_FEATURE_CMP_LEGACY,  '' core multi-processing legacy mode */
  142.  CPU_FEATURE_SVM,  '' AMD Secure virtual machine */
  143.  CPU_FEATURE_ABM,  '' LZCNT instruction support */
  144.  CPU_FEATURE_MISALIGNSSE, '' Misaligned SSE supported */
  145.  CPU_FEATURE_SSE4A,  '' SSE 4a from AMD */
  146.  CPU_FEATURE_3DNOWPREFETCH,  '' PREFETCH/PREFETCHW support */
  147.  CPU_FEATURE_OSVW,  '' OS Visible Workaround (AMD) */
  148.  CPU_FEATURE_IBS,  '' Instruction-based sampling */
  149.  CPU_FEATURE_SSE5,  '' SSE 5 instructions supported (deprecated, will never be 1) */
  150.  CPU_FEATURE_SKINIT,  '' SKINIT / STGI supported */
  151.  CPU_FEATURE_WDT,  '' Watchdog timer support */
  152.  CPU_FEATURE_TS,   '' Temperature sensor */
  153.  CPU_FEATURE_FID,  '' Frequency ID control */
  154.  CPU_FEATURE_VID,  '' Voltage ID control */
  155.  CPU_FEATURE_TTP,  '' THERMTRIP */
  156.  CPU_FEATURE_TM_AMD,  '' AMD-specified hardware thermal control */
  157.  CPU_FEATURE_STC,  '' Software thermal control */
  158.  CPU_FEATURE_100MHZSTEPS, '' 100 MHz multiplier control */
  159.  CPU_FEATURE_HWPSTATE,  '' Hardware P-state control */
  160.  CPU_FEATURE_CONSTANT_TSC,  '' TSC ticks at constant rate */
  161.  CPU_FEATURE_XOP,  '' The XOP instruction set (same as the old CPU_FEATURE_SSE5) */
  162.  CPU_FEATURE_FMA3,  '' The FMA3 instruction set */
  163.  CPU_FEATURE_FMA4,  '' The FMA4 instruction set */
  164.  CPU_FEATURE_TBM,  '' Trailing bit manipulation instruction support */
  165.  CPU_FEATURE_F16C,  '' 16-bit FP convert instruction support */
  166.  CPU_FEATURE_RDRAND,     '' RdRand instruction */
  167.  CPU_FEATURE_X2APIC,     '' x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) also see standard level 0000_000Bh */
  168.  CPU_FEATURE_CPB,  '' Core performance boost */
  169.  CPU_FEATURE_APERFMPERF,  '' MPERF/APERF MSRs support */
  170.  CPU_FEATURE_PFI,  '' Processor Feedback Interface support */
  171.  CPU_FEATURE_PA,   '' Processor accumulator */
  172.  CPU_FEATURE_AVX2,  '' AVX2 instructions */
  173.  CPU_FEATURE_BMI1,  '' BMI1 instructions */
  174.  CPU_FEATURE_BMI2,  '' BMI2 instructions */
  175.  CPU_FEATURE_HLE,  '' Hardware Lock Elision prefixes */
  176.  CPU_FEATURE_RTM,  '' Restricted Transactional Memory instructions */
  177.  CPU_FEATURE_AVX512F,  '' AVX-512 Foundation */
  178.  CPU_FEATURE_AVX512DQ,  '' AVX-512 Double/Quad granular insns */
  179.  CPU_FEATURE_AVX512PF,  '' AVX-512 Prefetch */
  180.  CPU_FEATURE_AVX512ER,  '' AVX-512 Exponential/Reciprocal */
  181.  CPU_FEATURE_AVX512CD,  '' AVX-512 Conflict detection */
  182.  CPU_FEATURE_SHA_NI,  '' SHA-1/SHA-256 instructions */
  183.  CPU_FEATURE_AVX512BW,  '' AVX-512 Byte/Word granular insns */
  184.  CPU_FEATURE_AVX512VL,  '' AVX-512 128/256 vector length extensions */
  185.  CPU_FEATURE_SGX,  '' SGX extensions. Non-autoritative, check cpu_id_t::sgx::present to verify presence */
  186.  CPU_FEATURE_RDSEED,  '' RDSEED instruction */
  187.  CPU_FEATURE_ADX,  '' ADX extensions (arbitrary precision) */
  188.  CPU_FEATURE_AVX512VNNI, '' AVX-512 Vector Neural Network Instructions */
  189.   CPU_FEATURE_AVX512VBMI, ''/*!< AVX-512 Vector Bit ManipulationInstructions (version 1) */
  190.   CPU_FEATURE_AVX512VBMI2, ''/*!< AVX-512 Vector Bit ManipulationInstructions (version 2) */
  191.   NUM_CPU_FEATURES
  192.  
  193. ' Private CPU_FEATURE_STRING As String[][] = [
  194. '   [CPU_FEATURE_FPU, "fpu"],
  195. '   [CPU_FEATURE_VME, "vme"],
  196. '   [CPU_FEATURE_DE, "de"],
  197. '   [CPU_FEATURE_PSE, "pse"],
  198. '   [CPU_FEATURE_TSC, "tsc"],
  199. '   [CPU_FEATURE_MSR, "msr"],
  200. '   [CPU_FEATURE_PAE, "pae"],
  201. '   [CPU_FEATURE_MCE, "mce"],
  202. '   [CPU_FEATURE_CX8, "cx8"],
  203. '   [CPU_FEATURE_APIC, "apic"],
  204. '   [CPU_FEATURE_MTRR, "mtrr"],
  205. '   [CPU_FEATURE_SEP, "sep"],
  206. '   [CPU_FEATURE_PGE, "pge"],
  207. '   [CPU_FEATURE_MCA, "mca"],
  208. '   [CPU_FEATURE_CMOV, "cmov"],
  209. '   [CPU_FEATURE_PAT, "pat"],
  210. '   [CPU_FEATURE_PSE36, "pse36"],
  211. '   [CPU_FEATURE_PN, "pn"],
  212. '   [CPU_FEATURE_CLFLUSH, "clflush"],
  213. '   [CPU_FEATURE_DTS, "dts"],
  214. '   [CPU_FEATURE_ACPI, "acpi"],
  215. '   [CPU_FEATURE_MMX, "mmx"],
  216. '   [CPU_FEATURE_FXSR, "fxsr"],
  217. '   [CPU_FEATURE_SSE, "sse"],
  218. '   [CPU_FEATURE_SSE2, "sse2"],
  219. '   [CPU_FEATURE_SS, "ss"],
  220. '   [CPU_FEATURE_HT, "ht"],
  221. '   [CPU_FEATURE_TM, "tm"],
  222. '   [CPU_FEATURE_IA64, "ia64"],
  223. '   [CPU_FEATURE_PBE, "pbe"],
  224. '   [CPU_FEATURE_PNI, "pni"],
  225. '   [CPU_FEATURE_PCLMUL, "pclmul"],
  226. '   [CPU_FEATURE_DTS64, "dts64"],
  227. '   [CPU_FEATURE_MONITOR, "monitor"],
  228. '   [CPU_FEATURE_DS_CPL, "ds_cpl"],
  229. '   [CPU_FEATURE_VMX, "vmx"],
  230. '   [CPU_FEATURE_SMX, "smx"],
  231. '   [CPU_FEATURE_EST, "est"],
  232. '   [CPU_FEATURE_TM2, "tm2"],
  233. '   [CPU_FEATURE_SSSE3, "ssse3"],
  234. '   [CPU_FEATURE_CID, "cid"],
  235. '   [CPU_FEATURE_CX16, "cx16"],
  236. '   [CPU_FEATURE_XTPR, "xtpr"],
  237. '   [CPU_FEATURE_PDCM, "pdcm"],
  238. '   [CPU_FEATURE_DCA, "dca"],
  239. '   [CPU_FEATURE_SSE4_1, "sse4_1"],
  240. '   [CPU_FEATURE_SSE4_2, "sse4_2"],
  241. '   [CPU_FEATURE_SYSCALL, "syscall"],
  242. '   [CPU_FEATURE_XD, "xd"],
  243. '   [CPU_FEATURE_X2APIC, "x2apic"],
  244. '   [CPU_FEATURE_MOVBE, "movbe"],
  245. '   [CPU_FEATURE_POPCNT, "popcnt"],
  246. '   [CPU_FEATURE_AES, "aes"],
  247. '   [CPU_FEATURE_XSAVE, "xsave"],
  248. '   [CPU_FEATURE_OSXSAVE, "osxsave"],
  249. '   [CPU_FEATURE_AVX, "avx"],
  250. '   [CPU_FEATURE_MMXEXT, "mmxext"],
  251. '   [CPU_FEATURE_3DNOW, "3dnow"],
  252. '   [CPU_FEATURE_3DNOWEXT, "3dnowext"],
  253. '   [CPU_FEATURE_NX, "nx"],
  254. '   [CPU_FEATURE_FXSR_OPT, "fxsr_opt"],
  255. '   [CPU_FEATURE_RDTSCP, "rdtscp"],
  256. '   [CPU_FEATURE_LM, "lm"],
  257. '   [CPU_FEATURE_LAHF_LM, "lahf_lm"],
  258. '   [CPU_FEATURE_CMP_LEGACY, "cmp_legacy"],
  259. '   [CPU_FEATURE_SVM, "svm"],
  260. '   [CPU_FEATURE_SSE4A, "sse4a"],
  261. '   [CPU_FEATURE_MISALIGNSSE, "misalignsse"],
  262. '   [CPU_FEATURE_ABM, "abm"],
  263. '   [CPU_FEATURE_3DNOWPREFETCH, "3dnowprefetch"],
  264. '   [CPU_FEATURE_OSVW, "osvw"],
  265. '   [CPU_FEATURE_IBS, "ibs"],
  266. '   [CPU_FEATURE_SSE5, "sse5"],
  267. '   [CPU_FEATURE_SKINIT, "skinit"],
  268. '   [CPU_FEATURE_WDT, "wdt"],
  269. '   [CPU_FEATURE_TS, "ts"],
  270. '   [CPU_FEATURE_FID, "fid"],
  271. '   [CPU_FEATURE_VID, "vid"],
  272. '   [CPU_FEATURE_TTP, "ttp"],
  273. '   [CPU_FEATURE_TM_AMD, "tm_amd"],
  274. '   [CPU_FEATURE_STC, "stc"],
  275. '   [CPU_FEATURE_100MHZSTEPS, "100mhzsteps"],
  276. '   [CPU_FEATURE_HWPSTATE, "hwpstate"],
  277. '   [CPU_FEATURE_CONSTANT_TSC, "constant_tsc"],
  278. '   [CPU_FEATURE_XOP, "xop"],
  279. '   [CPU_FEATURE_FMA3, "fma3"],
  280. '   [CPU_FEATURE_FMA4, "fma4"],
  281. '   [CPU_FEATURE_TBM, "tbm"],
  282. '   [CPU_FEATURE_F16C, "f16c"],
  283. '   [CPU_FEATURE_RDRAND, "rdrand"],
  284. '   [CPU_FEATURE_CPB, "cpb"],
  285. '   [CPU_FEATURE_APERFMPERF, "aperfmperf"],
  286. '   [CPU_FEATURE_PFI, "pfi"],
  287. '   [CPU_FEATURE_PA, "pa"],
  288. '   [CPU_FEATURE_AVX2, "avx2"],
  289. '   [CPU_FEATURE_BMI1, "bmi1"],
  290. '   [CPU_FEATURE_BMI2, "bmi2"],
  291. '   [CPU_FEATURE_HLE, "hle"],
  292. '   [CPU_FEATURE_RTM, "rtm"],
  293. '   [CPU_FEATURE_AVX512F, "avx512f"],
  294. '   [CPU_FEATURE_AVX512DQ, "avx512dq"],
  295. '   [CPU_FEATURE_AVX512PF, "avx512pf"],
  296. '   [CPU_FEATURE_AVX512ER, "avx512er"],
  297. '   [CPU_FEATURE_AVX512CD, "avx512cd"],
  298. '   [CPU_FEATURE_SHA_NI, "sha_ni"],
  299. '   [CPU_FEATURE_AVX512BW, "avx512bw"],
  300. '   [CPU_FEATURE_AVX512VL, "avx512vl"],
  301. '   [CPU_FEATURE_SGX, "sgx"],
  302. '   [CPU_FEATURE_RDSEED, "rdseed"],
  303. '   [CPU_FEATURE_ADX, "adx"],
  304. '   [CPU_FEATURE_AVX512VNNI, "avx512vnni"],
  305. '   [CPU_FEATURE_AVX512VBMI, "avx512vbmi"],
  306. '   [CPU_FEATURE_AVX512VBMI2, "avx512vbmi2"]
  307. ' ]
  308.  
  309. Private CPU_FLAGS_SHORT As String[][] = [
  310.   [CPU_FEATURE_MMX, "MMX"],
  311.   [CPU_FEATURE_MMXEXT, "(+)"],
  312.   [CPU_FEATURE_3DNOW, "3DNOW!"],
  313.   [CPU_FEATURE_3DNOWEXT, "(+)"],
  314.   [CPU_FEATURE_SSE, "SSE(1"],
  315.   [CPU_FEATURE_SSE2, "2"],
  316.   [CPU_FEATURE_PNI, "3"],
  317.   [CPU_FEATURE_SSSE3, "3S"],
  318.   [CPU_FEATURE_SSE4_1, "4.1"],
  319.   [CPU_FEATURE_SSE4_2, "4.2"],
  320.   [CPU_FEATURE_SSE4A, "4A"],
  321.   [CPU_FEATURE_SSE, ")"],
  322.   [CPU_FEATURE_XOP, "XOP"],
  323.   [CPU_FEATURE_AVX, "AVX(1"],
  324.   [CPU_FEATURE_AVX2, "2"],
  325.   [CPU_FEATURE_AVX512F, "512"],
  326.   [CPU_FEATURE_AVX, ")"],
  327.   [CPU_FEATURE_FMA3, "FMA(3"],
  328.   [CPU_FEATURE_FMA4, "4"],
  329.   [CPU_FEATURE_FMA3, ")"],
  330.   [CPU_FEATURE_AES, "AES"],
  331.   [CPU_FEATURE_PCLMUL, "CLMUL"],
  332.   [CPU_FEATURE_RDRAND, "RdRand"],
  333.   [CPU_FEATURE_SHA_NI, "SHA"],
  334.   [CPU_FEATURE_SGX, "SGX"],
  335.   [CPU_FEATURE_VMX, "VT-x"],
  336.   [CPU_FEATURE_SVM, "AMD-V"],
  337.   [CPU_FEATURE_LM, "x86-64"]
  338. ]
  339.  
  340. Public Enum VENDOR_INTEL = 0,   ''/*!< Intel CPU */
  341.   VENDOR_AMD,                   ''/*!< AMD CPU */
  342.   VENDOR_CYRIX,                 ''/*!< Cyrix CPU */
  343.   VENDOR_NEXGEN,                ''/*!< NexGen CPU */
  344.   VENDOR_TRANSMETA,             ''/*!< Transmeta CPU */
  345.   VENDOR_UMC,                   ''/*!< x86 CPU by UMC */
  346.   VENDOR_CENTAUR,               ''/*!< x86 CPU by IDT */
  347.   VENDOR_RISE,                  ''/*!< x86 CPU by Rise Technology */
  348.   VENDOR_SIS,                   ''/*!< x86 CPU by SiS */
  349.   VENDOR_NSC,                   ''/*!< x86 CPU by National Semiconductor */
  350.   VENDOR_HYGON,                ''/*!< Hygon CPU */
  351.   NUM_CPU_VENDORS,              ''/*!< Valid CPU vendor ids: 0..NUM_CPU_VENDORS - 1 */
  352.   VENDOR_UNKNOWN = -1
  353.  
  354. Public Enum INTEL_SGX1,         ''/*!< SGX1 instructions support */
  355.             INTEL_SGX2,         ''/*!< SGX2 instructions support */
  356.             NUM_SGX_FEATURES
  357.  
  358. Private cpu_vendor_string As String[] = ["GenuineIntel",
  359.   "AuthenticAMD",
  360.   "CyrixInstead",
  361.   "NexGenDriven",
  362.   "GenuineTMx86",
  363.   "UMC UMC UMC ",
  364.   "CentaurHauls",
  365.   "RiseRiseRise",
  366.   "SiS SiS SiS ",
  367.   "Geode by NSC",
  368.   "HygonGenuine"]
  369.  
  370. Public manufacturer_name As String[] = ["Intel",
  371.   "AMD",
  372.   "Cyrix",
  373.   "NexGen",
  374.   "Transmeta",
  375.   "UMC",
  376.   "Centaur",
  377.   "Rise",
  378.   "SiS",
  379.   "Geode",
  380.   "Hygon"]
  381.  
  382. Public Struct cpu_list_t
  383.   num_entries As Integer
  384.   names[200] As Pointer
  385. End Struct
  386.  
  387. Public Struct cpu_raw_data_t
  388.   basic_cpuid[32, 4] As Integer
  389.   ext_cpuid[32, 4] As Integer
  390.   intel_fn4[8, 4] As Integer
  391.   intel_fn11[4, 4] As Integer
  392.   intel_fn12h[4, 4] As Integer
  393.   intel_fn14h[4, 4] As Integer
  394.   amd_fn8000001dh[4, 4] As Integer
  395. End Struct
  396.  
  397. Public Struct cpu_mark_t
  398.   tsc As Long
  399.   sys_clock As Long
  400. End Struct
  401.  
  402. Public Struct cpu_epc_t
  403.   start_addr As Long
  404.   length As Long
  405. End Struct
  406.  
  407. Private Extern cpuid_present() As Integer
  408. Private Extern cpuid_lib_version() As String
  409. Private Extern get_total_cpus() As Integer
  410. Private Extern cpuid_get_raw_data(raw As Cpu_raw_data_t) As Integer
  411.  
  412. ''int cpuid_serialize_raw_data(struct cpu_raw_data_t* data, const char* filename);
  413. ''int cpuid_deserialize_raw_data(struct cpu_raw_data_t* data, const char* filename);
  414.  
  415. Private Extern cpuid_error() As String
  416. Private Extern cpu_identify(raw As Cpu_raw_data_t, data As Cpu_id_t) As Integer
  417.  
  418. ' /**
  419. '  * @brief Returns the short textual representation of a CPU architecture
  420. '  * @param architecture - the architecture, whose textual representation is wanted.
  421. '  * @returns a constant string like "x86", "ARM", etc.
  422. '  */
  423. ' const char* cpu_architecture_str(cpu_architecture_t architecture);
  424. ''Public Extern cpu_architecture_str(architecture As Integer) As String
  425.  
  426. Public Extern cpu_tsc_mark(mark As Cpu_mark_t)
  427. Public Extern cpu_tsc_unmark(mark As Cpu_mark_t)
  428. ''int cpu_clock_by_mark(struct cpu_mark_t * mark);
  429. Public Extern cpu_clock_by_mark(mark As Cpu_mark_t)
  430. Public Extern cpu_clock() As Integer
  431. Public Extern cpu_clock_by_os() As Integer
  432. Public Extern cpu_clock_by_ic(millis As Integer, runs As Integer) As Integer
  433. Public Extern cpu_clock_measure(millis As Integer, quad_check As Integer) As Integer
  434. Public Extern cpu_feature_str(feature As Integer) As String
  435. Private Extern cpuid_get_cpu_list(vendor As Integer, cpu_list As Cpu_list_t) As Integer
  436. Private Extern cpuid_free_cpu_list(cpu_list As Cpu_list_t)
  437. 'void cpuid_get_cpu_list(cpu_vendor_t vendor, struct cpu_list_t* list)
  438. Public mark As New Cpu_mark_t
  439. Public data As New Cpu_id_t
  440. Public data_flags As Pointer
  441.  
  442. Property Read cpuflags_short As String
  443. Private Function cpuflags_short_Read() As String
  444.   Dim short_flags As String
  445.   Dim i, z As Integer
  446.   For z = 0 To CPU_FLAGS_SHORT.Max
  447.     For i = 0 To NUM_CPU_FEATURES - 1
  448.       If Byte@(data_flags + (i + 84)) > 0 Then
  449.         If CPU_FLAGS_SHORT[z][0] = i Then
  450.           short_flags &= CPU_FLAGS_SHORT[z][1] & " "
  451.         Endif
  452.       Endif
  453.     Next
  454.   Next
  455.  
  456.   clean()
  457.   Return short_flags
  458. End
  459.  
  460. Public Sub _init()
  461.  
  462.   Dim raw As New Cpu_raw_data_t
  463.   ''Dim mark As New Cpu_mark_t
  464.   Dim datas As New Cpu_list_t
  465.   Dim au As String
  466.  
  467.   Dim fl As File
  468.  
  469.   If Not cpuid_present() Then Error.Raise("Sorry, your CPU doesn't support CPUID !")
  470.  
  471.   If cpuid_get_raw_data(raw) < 0 Then
  472.     Error.Raise("Sorry, cannot get the CPUID raw data.\nError: " & cpuid_error())
  473.   Endif
  474.   data = Alloc(SizeOf(gb.Byte), 512)
  475.   data_flags = Alloc(SizeOf(gb.Byte), 512)
  476.   If cpu_identify(raw, data) < 0 And cpu_identify(raw, data_flags) < 0 Then
  477.     Error.Raise("Sorry, CPU identification failed.\nError: " & cpuid_error())
  478.   Endif
  479.  
  480.   ''cpu_tsc_mark(mark)
  481.   ''Wait 0.10
  482.   ''cpu_tsc_unmark(mark)
  483.   ''cpu_clock_by_mark(mark)
  484.  
  485.   ' If (data.sgx.present) Then
  486.   '   Print Subst("SGX max enclave size (32-bit): &1", data.sgx.max_enclave_32bit)
  487.   '   Print Subst("SGX max enclave size (64-bit): &1", data.sgx.max_enclave_64bit)
  488.   '   Print Subst("SGX1 extensions              : &1 &2", data.sgx.flags[INTEL_SGX1], IIf(data.sgx.flags[INTEL_SGX1], "present", "absent"))
  489.   '   Print Subst("SGX2 extensions              : &1 &2", data.sgx.flags[INTEL_SGX2], IIf(data.sgx.flags[INTEL_SGX2], "present", "absent"))
  490.   '   Print Subst("SGX MISCSELECT               : &1", data.sgx.misc_select)
  491.   '   Print Subst("SGX SECS.ATTRIBUTES mask     : &1", data.sgx.secs_attributes)
  492.   '   Print Subst("SGX SECS.XSAVE feature mask  : &1", data.sgx.secs_xfrm)
  493.   '   Print Subst("SGX EPC sections count       : &1", data.sgx.num_epc_sections)
  494.   ' Endif
  495.  
  496.   Try LIBCPUID_VERSION = cpuid_lib_version()
  497.   If Error Then LIBCPUID_VERSION = "<Unknown>"
  498.   ' Print ""; IIf(gb.BigEndian, "BigEndian", "LittleEndian")
  499.   ' Print ""; IIf(gb.LittleEndian, "LittleEndian", "BigEndian")
  500.   Print "CPUID is "; IIf(cpuid_present(), "present", "absent")
  501.   Print "CPU Info:"
  502.   Print "------------------"
  503.   Print "  vendor_str : "; String@(data.vendor_str.Data) '' cpu_vendor_string[data.vendor]
  504.   Print "  manufaturer: "; manufacturer_name[data.vendor]
  505.   Print "  vendor id  : "; (data.vendor)
  506.   Print "  brand_str  : "; String@(data.brand_str.data)
  507.   Print "  family     : "; data.family
  508.   Print "  model      : "; data.model
  509.   Print "  stepping   : "; data.stepping
  510.   ' Print "  ext_family : "; data.ext_family
  511.   ' Print "  ext_model  : "; data.ext_model
  512.   ' Print "  num_cores  : "; data.num_cores
  513.   ' Print "  num_logical: "; data.num_logical_cpus
  514.   ' Print "  tot_logical: "; data.total_logical_cpus
  515.   '
  516.   ' Print "  L1 D cache : "; data.l1_data_cache; " KB"
  517.   ' Print "  L1 I cache : "; data.l1_instruction_cache; " KB"
  518.   '
  519.   ' Print "  L2 cache   : "; data.l2_cache; " KB"
  520.   ' Print "  L3 cache   : "; data.l3_cache; " KB"
  521.   ' Print "  L4 cache   : "; data.l4_cache; " KB"
  522.   '
  523.   ' Print "  L1 assoc. : "; data.l1_assoc; "-way"
  524.   ' Print "  L1D assoc. : "; data.l1_data_assoc; "-way"
  525.   ' Print "  L1I assoc. : "; data.l1_instruction_assoc; "-way"
  526.   '
  527.   ' Print "  L2 assoc.  : "; data.l2_assoc; "-way"
  528.   ' Print "  L3 assoc.  : "; data.l3_assoc; "-way"
  529.   ' Print "  L4 assoc.  : "; data.l4_assoc; "-way"
  530.   '
  531.   ' Print "  L1C line sz: "; data.l1_cacheline; " bytes"
  532.   ' Print "  L1D line sz: "; data.l1_data_cacheline; " bytes"
  533.   ' Print "  L1I line sz: "; data.l1_instruction_cacheline; " bytes"
  534.   '
  535.   ' Print "  L2 line sz : "; data.l2_cacheline; " bytes"
  536.   ' Print "  L3 line sz : "; data.l3_cacheline; " bytes"
  537.   ' Print "  L4 line sz : "; data.l4_cacheline; " bytes"
  538.   Print "  SSE units  : "; data.sse_size; " bit "; IIf(data.detection_hints[CPU_HINT_SSE_SIZE_AUTH], "(authoritative)", "(non-authoritative)")
  539.   Print "  code name  : "; String@(data.cpu_codename.data)
  540.   ' Print "  Supported features   : ";
  541.  
  542.   ' For i = 0 To NUM_CPU_FEATURES - 1
  543.   ' If Byte@(data_flags + (i + 84)) > 0 Then
  544.   '   For z = 0 To CPU_FLASGS_SHORT.Max
  545.   '     If i = CPU_FLASGS_SHORT[z][0] Then
  546.   '       Print CPU_FLASGS_SHORT[z][i]
  547.   '     Endif
  548.   '   Next
  549.   '   If cpu_feature_str(CPU_FEATURE_SSE) = cpu_feature_str(i) Then
  550.   '     Print " "; cpu_feature_str(i);
  551.   '   Endif
  552.   ' Endif
  553.  
  554.   ''Print "   \"FEATURE\":           "; cpu_feature_str(i); IIf(Byte@(data_flags + (i + 84)), " Present", " Absent");
  555.   'Next
  556.   '  Print "\n"
  557.   '  Print "  Unsupported features   : ";
  558.   ' Dim i As Integer
  559.   ' For i = 0 To NUM_CPU_FEATURES
  560.   '
  561.   '    If Byte@(data_flags + (i + 84)) = 1 Then
  562.   '      Print " "; cpu_feature_str(i);
  563.   '    Endif
  564.   ' '  
  565.   ' '   Print "   \"FEATURE\":           "; cpu_feature_str(i); IIf(Byte@(data_flags + (i + 84)), " Present", " Absent");
  566.   ' '   Print "\n"
  567.   ' Next
  568.  
  569.   'Free(data_flags)
  570.  
  571.   ' Print "   \"CPU_CLOCK\":          "; cpu_clock(); " Mhz"
  572.   ' Print "   \"CPU_CLOCK_BY_OS\":    "; cpu_clock_by_os(); " Mhz"
  573.   ' Print "   \"CPU_CLOCK_BY_IC\":    "; cpu_clock_by_ic(25, 16); " Mhz"
  574.   ' Print "   \"CPU_CLOCK_MEASURE\":  "; cpu_clock_measure(400, 1); " Mhz"
  575.   ' Print "   \"MARK_TSC\":           "; mark.tsc
  576.   ' Print "   \"MARK_SYS_CLOCK\":     "; mark.sys_clock
  577.  
  578.   ' For i = 0 To 124
  579.   ' If data.flags[i] >= &h1 Then
  580.   '   Print cpu_feature_str(i); " ";
  581.   ' Endif
  582.   '  ''Print "   \"FEATURE\":           "; cpu_feature_str(i); IIf((data.flags[i] >= &h1), " Present", " Absent")
  583.   ' Next
  584.   'For i = 0 To NUM_CPU_FEATURES - 1
  585.   'Print cpu_feature_str(CPU_FEATURE_LM) & " || " & IIf(Byte@(data_flags + (CPU_FEATURE_LM + 84)), " Present", " Absent")
  586.   'Next
  587.   ' Print NUM_CPU_FEATURES
  588.   ''Free(data_flags)
  589.   ''Free(data)
  590. End
  591.  
  592.  
  593.  
  594. Private Function HT_Read() As String[]
  595.  
  596.   Select Case Libcpuid.data.vendor
  597.    
  598.     Case VENDOR_INTEL
  599.       If Byte@(data_flags + (CPU_FEATURE_HT + 84)) = 1 Then
  600.         Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
  601.       Else If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
  602.         Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
  603.       Else If Exist("/sys/devices/system/cpu/smt/") = True Then
  604.         Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
  605.       Else
  606.         Return ["Hyper-Threading:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  607.       Endif
  608.      
  609.     Case VENDOR_AMD
  610.       If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
  611.         Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
  612.       Else If Exist("/sys/devices/system/cpu/smt/") = True Then
  613.         Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
  614.       Else
  615.         Return ["Hyper-Transport:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  616.       Endif
  617.      
  618.   End Select
  619.  
  620.  
  621.   ' If Byte@(Libcpuid.data_flags + (Libcpuid.CPU_FEATURE_HT + 84)) = 1 Then
  622.   '   If Libcpuid.data.vendor = Libcpuid.VENDOR_INTEL Then
  623.   '     Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
  624.   '   Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
  625.   '     Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
  626.   '   Endif
  627.   ' Else If (Libcpuid.data.total_logical_cpus = Libcpuid.data.num_cores) = False Then
  628.   '   If Libcpuid.data.vendor = Libcpuid.VENDOR_INTEL Then
  629.   '     Return ["Hyper-Threading:", True, ".public/48x48/emblems/emblem-default.svg"]
  630.   '   Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
  631.   '     Return ["Hyper-Transport:", True, ".public/48x48/emblems/emblem-default.svg"]
  632.   '   Endif
  633.   ' Else If Libcpuid.data.vendor = VENDOR_INTEL Then
  634.   '   Return ["Hyper-Threading:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  635.   ' Else If Libcpuid.data.vendor = Libcpuid.VENDOR_AMD Then
  636.   '   Return ["Hyper-Transport:", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  637.   ' Endif
  638.  
  639. End
  640.  
  641. Private Function VIRTUALIZATION_Read() As String[]
  642.   If Byte@(data_flags + (CPU_FEATURE_VMX + 84)) Then
  643.     Return ["Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
  644.   Else If Byte@(data_flags + (CPU_FEATURE_SVM) + 84) Then
  645.     Return ["HW Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
  646.   Else If Exist("/dev/kvm") = True Then
  647.     Return ["HW Virtualization", True, ".public/48x48/emblems/emblem-default.svg"]
  648.   Else
  649.     Return ["HW Virtualization", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  650.   Endif
  651. End
  652. 'CPU_FEATURE_NX
  653. 'CPU_FEATURE_XD
  654. 'CPU_FEATURE_LM
  655.  
  656. Private Function BITEXTENSIONS_Read() As String[]
  657.   If Byte@((data_flags + (CPU_FEATURE_LM + 84))) Then
  658.     Return ["X86-64 Bit Ext", True, ".public/48x48/emblems/emblem-default.svg"]
  659.   Else
  660.     Return ["X86-64 Bit Ext", False, ".public/48x48/emblems/emblem-unreadable.svg"]
  661.   Endif
  662. End
  663.  
  664. Public Sub clean()
  665.  
  666.   Free(data_flags)
  667.  
  668. End
  669.  
  670. Private Function VERSION_CPUID_LIB_Read() As String
  671.  
  672.   Return LIBCPUID_VERSION
  673.  
  674. End
Tags: Gambas
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