`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   12:21:44 01/09/2012
// Design Name:   cpu6
// Module Name:   D:/Uczelnia/Systemy Wbudowane/cpu6/cpu6_testbench.v
// Project Name:  CPU6
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cpu6
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module cpu6_testbench;

    // Inputs
    reg clk;
    reg rst;
    reg INT;
    reg [7:0] PORTA_in;

    // Outputs
    wire [7:0] PORTA_out;

    // Instantiate the Unit Under Test (UUT)
    cpu6 uut (
        .clk(clk),
        .rst(rst),
        .INT(INT),
        .PORTA_out(PORTA_out),
        .PORTA_in(PORTA_in)
    );
    localparam T = 20;

    always
        begin
            clk = 1'b0;
            #(T/2);
            clk = 1'b1;
            #(T/2);
        end

    initial
        begin
            rst = 1'b0;
            #(T);
            rst = 1'b1;
        end

    initial begin

        INT = 1;
        PORTA_in = 8'b00000001;

        #100;
        INT = 0;
        #80;

        PORTA_in = 8'b11111111;

        #100;
        INT = 0;
        PORTA_in = 8'b00001001;

        #100;

    end

endmodule