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  1. *** MCA Error Report ***
  2. CPU Machine Check Architecture Error Dump (CPU: Intel(R) Core(TM) i5-6267U CPU @ 2.90GHz, CPUID: 0x406E3)
  3. Core: 0
  4. IA32_MC3_STATUS=0xFE00000000800400
  5. IA32_MC3_CTL=0x0
  6. IA32_MC3_ADDR=0xFFFFF8056D3F72D8
  7. IA32_MC3_MISC=0xFFFFF8056D3F72D8
  8. Core: 0
  9. IA32_MC4_STATUS=0xFE00000000800400
  10. IA32_MC4_CTL=0x0
  11. IA32_MC4_ADDR=0xFFFFF8056D3F1363
  12. IA32_MC4_MISC=0xFFFFF8056D3F1363
  13. Core: 1
  14. IA32_MC3_STATUS=0xFE00000000800400
  15. IA32_MC3_CTL=0x1F
  16. IA32_MC3_ADDR=0xFFFFF8056D3F72D8
  17. IA32_MC3_MISC=0xFFFFF8056D3F72D8
  18. Core: 2 3
  19. IA32_MC3_STATUS=0xFE00000000800400
  20. IA32_MC3_CTL=0x1F
  21. IA32_MC3_ADDR=0xFFFFF8056D3F1363
  22. IA32_MC3_MISC=0xFFFFF8056D3F1363
  23.  
  24.  
  25. *** Device Tree ***
  26. {
  27. "pcie_cfg_base" : "0xe0000000",
  28. "pci_devices" :
  29. {
  30. "0x0" : "MCHC@0",
  31. "0x10000" : "IGPU@2",
  32. "0xa0000" : "XHC1@14",
  33. "0xc8000" : "URT2@19",
  34. "0xb0000" : "IMEI@16",
  35. "0xe0000" : "RP01@1C",
  36. "0xe4000" : "RP05@1C,4",
  37. "0xe8000" : "RP09@1D",
  38. "0xeb000" : "RP12@1D,3",
  39. "0x100000" : "RP01@1C/IOPP/SSD0@0",
  40. "0xf0000" : "URT0@1E",
  41. "0xf1000" : "URT1@1E,1",
  42. "0xf3000" : "SPI1@1E,3",
  43. "0x200000" : "RP12@1D,3/IOPP/ARPT@0",
  44. "0xf8000" : "LPCB@1F",
  45. "0xfa000" : "PMCR@1F,2",
  46. "0xfb000" : "HDEF@1F,3",
  47. "0xfc000" : "SBUS@1F,4",
  48. "0x8200000" : "RP05@1C,4/IOPP/UPSB@0",
  49. "0x300000" : "RP09@1D/IOPP/UPSB@0",
  50. "0x8300000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB0@0",
  51. "0x8308000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB1@1",
  52. "0x400000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB0@0",
  53. "0x408000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB1@1",
  54. "0x8310000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB2@2",
  55. "0x8320000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB4@4",
  56. "0x410000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB2@2",
  57. "0x420000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB4@4",
  58. "0x8400000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB2@2/IOPP/XHC2@0",
  59. "0x8500000" : "RP05@1C,4/IOPP/UPSB@0/IOPP/DSB0@0/IOPP/NHI0@0",
  60. "0x500000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB2@2/IOPP/XHC3@0",
  61. "0x600000" : "RP09@1D/IOPP/UPSB@0/IOPP/DSB0@0/IOPP/NHI0@0"
  62. },
  63. "device_mmio" :
  64. {
  65. "PCI0@0" :
  66. [
  67. { "a" : "0xcf8", "s" : "0x8" }
  68. ],
  69. "PCI0@0/AppleACPIPCI/IGPU@2" :
  70. [
  71. { "a" : "0x7f90000000", "s" : "0x1000000" },
  72. { "a" : "0x7f80000000", "s" : "0x10000000" }
  73. ],
  74. "PCI0@0/AppleACPIPCI/XHC1@14" :
  75. [
  76. { "a" : "0x7f91010000", "s" : "0x10000" }
  77. ],
  78. "PCI0@0/AppleACPIPCI/IMEI@16" :
  79. [
  80. { "a" : "0x7f91028000", "s" : "0x1000" }
  81. ],
  82. "PCI0@0/AppleACPIPCI/URT2@19" :
  83. [
  84. { "a" : "0x7f91027000", "s" : "0x1000" }
  85. ],
  86. "PCI0@0/AppleACPIPCI/RP01@1C/IOPP/SSD0@0" :
  87. [
  88. { "a" : "0x82500000", "s" : "0x4000" }
  89. ],
  90. "PCI0@0/AppleACPIPCI/RP05@1C,4/IOPP/UPSB@0/IOPP/DSB0@0/IOPP/NHI0@0" :
  91. [
  92. { "a" : "0x82800000", "s" : "0x40000" },
  93. { "a" : "0x82840000", "s" : "0x1000" }
  94. ],
  95. "PCI0@0/AppleACPIPCI/RP05@1C,4/IOPP/UPSB@0/IOPP/DSB2@2/IOPP/XHC2@0" :
  96. [
  97. { "a" : "0x82700000", "s" : "0x10000" }
  98. ],
  99. "PCI0@0/AppleACPIPCI/RP09@1D/IOPP/UPSB@0/IOPP/DSB0@0/IOPP/NHI0@0" :
  100. [
  101. { "a" : "0xaab00000", "s" : "0x40000" },
  102. { "a" : "0xaab40000", "s" : "0x1000" }
  103. ],
  104. "PCI0@0/AppleACPIPCI/RP09@1D/IOPP/UPSB@0/IOPP/DSB2@2/IOPP/XHC3@0" :
  105. [
  106. { "a" : "0xaaa00000", "s" : "0x10000" }
  107. ],
  108. "PCI0@0/AppleACPIPCI/RP12@1D,3/IOPP/ARPT@0" :
  109. [
  110. { "a" : "0x82400000", "s" : "0x8000" },
  111. { "a" : "0x82000000", "s" : "0x400000" }
  112. ],
  113. "PCI0@0/AppleACPIPCI/URT0@1E" :
  114. [
  115. { "a" : "0x7f91026000", "s" : "0x1000" }
  116. ],
  117. "PCI0@0/AppleACPIPCI/URT1@1E,1" :
  118. [
  119. { "a" : "0x7f91025000", "s" : "0x1000" }
  120. ],
  121. "PCI0@0/AppleACPIPCI/SPI1@1E,3" :
  122. [
  123. { "a" : "0x7f91024000", "s" : "0x1000" }
  124. ],
  125. "PCI0@0/AppleACPIPCI/PMCR@1F,2" :
  126. [
  127. { "a" : "0x82624000", "s" : "0x4000" }
  128. ],
  129. "PCI0@0/AppleACPIPCI/HDEF@1F,3" :
  130. [
  131. { "a" : "0x7f91020000", "s" : "0x4000" },
  132. { "a" : "0x7f91000000", "s" : "0x10000" }
  133. ],
  134. "PCI0@0/AppleACPIPCI/SBUS@1F,4" :
  135. [
  136. { "a" : "0x7f91029000", "s" : "0x100" }
  137. ],
  138. "DMAC" :
  139. [
  140. { "a" : "0x0", "s" : "0x20" },
  141. { "a" : "0x81", "s" : "0x11" },
  142. { "a" : "0x93", "s" : "0xd" },
  143. { "a" : "0xc0", "s" : "0x20" }
  144. ],
  145. "FWHD" :
  146. [
  147. { "a" : "0xff000000", "s" : "0x1000000" }
  148. ],
  149. "IPIC" :
  150. [
  151. { "a" : "0x20", "s" : "0x2" },
  152. { "a" : "0x24", "s" : "0x2" },
  153. { "a" : "0x28", "s" : "0x2" },
  154. { "a" : "0x2c", "s" : "0x2" },
  155. { "a" : "0x30", "s" : "0x2" },
  156. { "a" : "0x34", "s" : "0x2" },
  157. { "a" : "0x38", "s" : "0x2" },
  158. { "a" : "0x3c", "s" : "0x2" },
  159. { "a" : "0xa0", "s" : "0x2" },
  160. { "a" : "0xa4", "s" : "0x2" },
  161. { "a" : "0xa8", "s" : "0x2" },
  162. { "a" : "0xac", "s" : "0x2" },
  163. { "a" : "0xb0", "s" : "0x2" },
  164. { "a" : "0xb4", "s" : "0x2" },
  165. { "a" : "0xb8", "s" : "0x2" },
  166. { "a" : "0xbc", "s" : "0x2" },
  167. { "a" : "0x4d0", "s" : "0x2" }
  168. ],
  169. "MATH" :
  170. [
  171. { "a" : "0xf0", "s" : "0x1" }
  172. ],
  173. "LDRC" :
  174. [
  175. { "a" : "0x2e", "s" : "0x2" },
  176. { "a" : "0x4e", "s" : "0x2" },
  177. { "a" : "0x61", "s" : "0x1" },
  178. { "a" : "0x63", "s" : "0x1" },
  179. { "a" : "0x65", "s" : "0x1" },
  180. { "a" : "0x67", "s" : "0x1" },
  181. { "a" : "0x80", "s" : "0x1" },
  182. { "a" : "0x92", "s" : "0x1" },
  183. { "a" : "0xb2", "s" : "0x2" },
  184. { "a" : "0xffff", "s" : "0x1" },
  185. { "a" : "0x1800", "s" : "0xff" },
  186. { "a" : "0x800", "s" : "0x80" }
  187. ],
  188. "RTC" :
  189. [
  190. { "a" : "0x70", "s" : "0x8" }
  191. ],
  192. "TIMR" :
  193. [
  194. { "a" : "0x40", "s" : "0x4" },
  195. { "a" : "0x50", "s" : "0x4" }
  196. ],
  197. "SMC" :
  198. [
  199. { "a" : "0x300", "s" : "0x20" },
  200. { "a" : "0xfef00000", "s" : "0x10000" }
  201. ],
  202. "EC" :
  203. [
  204. { "a" : "0x62", "s" : "0x1" },
  205. { "a" : "0x66", "s" : "0x1" }
  206. ],
  207. "PDRC" :
  208. [
  209. { "a" : "0xfed10000", "s" : "0x8000" },
  210. { "a" : "0xfed18000", "s" : "0x1000" },
  211. { "a" : "0xfed19000", "s" : "0x1000" },
  212. { "a" : "0xe0000000", "s" : "0x10000000" },
  213. { "a" : "0xfed20000", "s" : "0x20000" },
  214. { "a" : "0xfed90000", "s" : "0x4000" },
  215. { "a" : "0xfed45000", "s" : "0x4b000" },
  216. { "a" : "0xff000000", "s" : "0x1000000" },
  217. { "a" : "0xfee00000", "s" : "0x100000" },
  218. { "a" : "0xfd000000", "s" : "0x1000000" },
  219. { "a" : "0xfe000000", "s" : "0x10000" },
  220. { "a" : "0xfe010000", "s" : "0x1000" },
  221. { "a" : "0xfe020000", "s" : "0x16000" },
  222. { "a" : "0xfe036000", "s" : "0x6000" },
  223. { "a" : "0xfe03c000", "s" : "0x1000" },
  224. { "a" : "0xfe03d000", "s" : "0x83000" },
  225. { "a" : "0xfe0c0000", "s" : "0x40000" },
  226. { "a" : "0xfe100000", "s" : "0x100000" },
  227. { "a" : "0xfe200000", "s" : "0x200000" },
  228. { "a" : "0xfe400000", "s" : "0x10000" },
  229. { "a" : "0xfe410000", "s" : "0x1f0000" },
  230. { "a" : "0xfe600000", "s" : "0x200000" }
  231. ],
  232. "MEM2" :
  233. [
  234. { "a" : "0x20000000", "s" : "0x200000" },
  235. { "a" : "0x40000000", "s" : "0x200000" }
  236. ]
  237. }
  238. }
  239.  
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