Whats New

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CCRs Fixed in Release 18.1 ISR4
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CCMPR02084455    Crash observed during saveDesign
CCMPR02081781    Tool crashes during oaIn
CCMPR02080914    Tool crash running verifyPowerDomain
CCMPR02080777    Trim to trim spacing violation
CCMPR02080736    Missing inserted routing trim on top of pre-defined cell trim OBS
CCMPR02080369    NRHF crash while routing 6K nets
CCMPR02079337    Tie cell addition fails for many pins after taking 15+ hours, keeps on applying GNCs in loop
CCMPR02078612    tQuantus is not honoring layer-based RC scaling on SEC10
CCMPR02078459    summaryReport -outDir does not output all files into the specified outdir
CCMPR02078420    addStripe with stapling style will not generate full expected for M4 in channel
CCMPR02077263    setTopCell command is crashing when invoked from GUI
CCMPR02076515    M2 EOL violation not flagged by verify_drc
CCMPR02076308    19.1 QOR degradation when compared to 18.12
CCMPR02076247    VIA2 spacing violations within Invs18.14
CCMPR02076099    saveDesign cannot override the starting DBS when setOaxMode -locking true
CCMPR02075786    verifyConnectivity detects open error at net accessing pins as feedthrough
CCMPR02075445    Power bump routing using fcroute
CCMPR02075239    ecoRoute in distributed mode flags false adjacent cut violations not seen in non-distributed mode
CCMPR02075154    Crash while NR starts routing of the clock nets during ccopt_design
CCMPR02074980    fcroute: shorts and opens
CCMPR02074966    fcroute taps wrong VSSO pin
CCMPR02074539    18.11-s100_1 crash when running "get_lib_clock_tree_path_delay"
CCMPR02074460    M1 routing under X1 trim layer
CCMPR02074069    addStripe causing segmentation fault when "-power_domains" is specified
CCMPR02073681    NRHF crash, CheckPinAccess
CCMPR02073423    CTD SEGV selecting "Constraints->dont touch" on clock mesh design
CCMPR02073380    delete_dangling_port introduces the error IMPSYC-1919
CCMPR02073245    SEGV during route_secondary_pg_pins in timing_driven
CCMPR02073054    _SADP_FILLS_RESERVED is written to Netlist
CCMPR02072971    DIAG during multibit merging in place_opt_design

CCMPR02072915    place_opt_design not honoring selective sizing for all the specified instances
CCMPR02072913    Incorrect error message for 'addStripe -power_domains' and inconsistent behavior between multi/single PD
CCMPR02072858    addStripe creates euclidean spacing violations to 45-degree edges of bumps
CCMPR02072754    Missing VIA definition in DEF
CCMPR02072685    ERROR: (internal tcl error) 'invalid command name "cbGet"
CCMPR02072146    place_opt_design crash
CCMPR02071682    addTieHiLo creates new net with empty props
CCMPR02071594    FlexILM for blocks does not show partition pins in Hierarchical DB when block pins have PLACED status
CCMPR02070851    PSW-enable In/Out pin are not in ALWAYS ON power domain
CCMPR02070725    Router hangs
CCMPR02069943    place_opt_design crash -place_detail_wire_length_opt_effort or -place_global_clock_power_driven_effort is high
CCMPR02069497    Crash during optDesign -postRoute on chip level
CCMPR02069267    ECF not able to identify all ICGs with multi driver net
CCMPR02069052    Problem of memory in deleteRouteBlk
CCMPR02068981    place_opt_design -place takes longer runtime during global placement
CCMPR02068721    CCOPT crash in cell filtering
CCMPR02068257    Crash during ecoRoute for FE Block
CCMPR02068129    Stack trace a flattenPartition
CCMPR02068057    refinePlace hanging again, not finding legal locations for cells due to "Other"
CCMPR02068045    colorizePowerMesh crashed with 18.14-e033_1
CCMPR02067384    displayScanChain does not work in an interactive session
CCMPR02067381    Unnecessary jogs during FlexH routing
CCMPR02066879    reportVtInstCount is giving stack trace
CCMPR02066708    High Runtime during detail route
CCMPR02066026    Stack trace at the start of Postroute while restoring markers from Route Db
CCMPR02065879    18.13e070 exits with the synthesize_flexible_htrees command without completing htree routes, errors with 18.13e050
CCMPR02065317    Route hangs
CCMPR02065062    Fail to route net in region. Set net to open
CCMPR02065046    Target Based Opt file has parsing error with bit slice name
CCMPR02064996    ccopt_design -cts stage crashes during the clustering stage
CCMPR02064583    ccopt_design hangs
CCMPR02064372    Detail routing initial DRC count is very high without the option '-routeEcoOnlyInLayers'
CCMPR02063566    Signoff extraction is not working in 18.13 & 17.16 - same scripts worked OK in 17.15
CCMPR02063550    route_details is resulting in false trim OBS short violations
CCMPR02063543    SEGV during editPowerVia
CCMPR02063528    NR is reporting off trim grid violations that are not real
CCMPR02063420    Error while restoring the design
CCMPR02062862    Long runtime of the editDelete -net command
CCMPR02062538    nanoRoute SEGV
CCMPR02062475    17.1 and 18.1: Crash in post-route opt (ccopt) from coePostCommitDelayUpdater/CompressedWave, ground voltage is not 0
CCMPR02062301    Buffering issue due to Iso cells missing in Innovus Stylus
CCMPR02061944    addFiller not able to insert double height cell
CCMPR02061887    addStripe breaks stripe at selected even when -break_at set to none when power domains exist in design
CCMPR02061828    Secondary PG pin routing setup does not get saved when Tie cells are not part of Prects Db
CCMPR02061821    Still difference between timing seen by optimization and timing command
CCMPR02061152    mesh_vias are not added on the top/bottom 2 rows
CCMPR02061150    Stack trace generated during check_design
CCMPR02060716    Stack trace while saving OA design after Routing (Stylus)
CCMPR02060711    Enhancement to enforce row numbers in block and between macros to be multiples of 4
CCMPR02060651    N/A reported in Expanded views if "ignorePathGroupsForHold {in2reg reg2out in2out default}" specified w/o creating the basic path group
CCMPR02060307    ccopt_design crashes
CCMPR02060288    CTS HTree crash
CCMPR02060249    optDesign -postRoute -drv long runtime
CCMPR02060201    Innovus is crashing during ecoRoute
CCMPR02060125    update_power_vias does not respect via11 blockage over m10 block pins but does over m10 stripes
CCMPR02060072    Inverting ICG scoring function too restrictive (follow on from CCR 1969990)
CCMPR02059995    Wrong design name saved in *.enc.dat/gui_pref.tcl
CCMPR02059644    ecoChangeCell in batch mode SEGV
CCMPR02059562    Wire gets dropped when writing OA db and reloading
CCMPR02059548    create_snapshot on restored placeopt DB creates massive timing
CCMPR02059434    Floorplan prediction in Genus calling Innovus 'planDesign' results in SEGV
CCMPR02059411    sroute SEGV during stripegen target
CCMPR02059053    addRepeaterByRule segv
CCMPR02058952    sroute moving ports in COVER status to outside the die
CCMPR02058873    Need to issue a warning message related to tech file error
CCMPR02058200    Crash after deleting a net
CCMPR02057772    DIAG [dbWireIO.c:1562:dbiNetNotNeedToSave] during saveDesign
CCMPR02057557    Clock route jogging on preferred routing layers using 18.14
CCMPR02057549    create_clock_tree_spec output file has typo
CCMPR02057514    Crash during global routing part of routeDesign with 18.71-e191
CCMPR02056738    Appending empty lef file list to init_lef_file causes saveDesign link every file in the current run dir
CCMPR02056633    Innovus crashing on SARC design during QRC extraction
CCMPR02055978    Crash during save design after refreshing upf, need freeTimingGraph
CCMPR02055946    Innovus command fcroute  crashes without giving any information
CCMPR02055226    PostRoute optDesign crashed during ecoRoute detailRoute
CCMPR02055209    routeDesign -highFrequency SEGV
CCMPR02055104    add_gui_shape or addCustomBox no longer allows user to manually resize using GUI due to fail of setObjFPlanBox
CCMPR02055067    18.13-e070_1 and 18.14 set is_memory to true even for all std cells when voltage scaling lib set is loaded
CCMPR02054599    SpecifyCellEdgeSpacing -underPG does not work as suggested
CCMPR02054386    Innovus calls refinePlace after disabling batchmode destroying timing
CCMPR02054105    Crash during the placeDesign command
CCMPR02053619    ecoSplitFlop crash
CCMPR02053080    CTS crashing at clustering with 17.15 version
CCMPR02051947    SEGV in post-cts opt in ccopt_design after area reclaim
CCMPR02051882    SEGV while running the verifyProcessAntenna command
CCMPR02051505    setEdit(inn1625) vs setEditMode(inn1812) compatibility ?
CCMPR02051463    get_ccopt_skew_group_delay crashed
CCMPR02051294    iQRC extraction crash at postroute
CCMPR02050791    Restoring CCOpt config while restoring the DB is taking long runtime
CCMPR02050703    Flexible htree image colormap change makes the data difficult to use
CCMPR02050480    Timing miscorrelation moving from tQuantus to iQuantus
CCMPR02050031    Htree net routed with min cut DRCs
CCMPR02049947    NR is not updating the default power domain dimension after switching partition
CCMPR02049931    place_opt_design crashes with set_limited_access_feature FlipFlopMergeAndSplit false
CCMPR02049229    Provide an option to allow floating pins to be placed at abutted edge BUT NOT abutting to other floating
CCMPR02048930    Synthesize flex htree crash because of wrong tracks
CCMPR02048381    attachTerm crash
CCMPR02048374    setDesignMode -node S5 causes huge jump in eGR congestion
CCMPR02048296    bind-key u/d/<num> does not work in edit route
CCMPR02048261    Innovus is crashed during checkPlace
CCMPR02047335    addWellTap is crashing in 18.12-s106_1
CCMPR02047140    add_stripes causing SEGV in 18.13-e050 and e070 but not 18.12-e053
CCMPR02047122    why via pillar gets replaced when the eco was only vt swapping
CCMPR02047048    streamOut: wrong min/max voltage text labels for 45-degree shapes
CCMPR02047021    Multiple Innovus GUI elements white font against light background making text illegible
CCMPR02046977    CTS handling of insts directly assigned to placement groups incorrect for power domains with multiple rectangles
CCMPR02046944    SEGV during assign_clock_tree_source_groups for a design with preserved ports v19.10-d235_1
CCMPR02046629    remove_assigns -net is removing assign statements on all the nets in the design
CCMPR02046570    ccopt_design causes SEGV during "Reducing clock tree power 1..."
CCMPR02046543    Crash and DIAG messages reported during filler decap insertion
CCMPR02046513    Crash reported during ecoRoute in 18.71-e153
CCMPR02046466    NanoRoute: Further improvement on fixing trim grid violations is needed for certification
CCMPR02046325    Tran violations reported with report_constraint and reportTranViolation have mismatch in postRoute
CCMPR02046088    DIAG during create_timing_budget
CCMPR02045997    saveNetlist creates wrong assign statement for the input port
CCMPR02045965    Customer reported Innovus SEGV while executing command editAddRoute
CCMPR02045849    Not able to build clock tree with in-bound cells
CCMPR02045449    editPowerVia - same mask metal aligned cuts
CCMPR02045427    place_opt_design crashes
CCMPR02045294    Global Opt QOR worse with compact GO flow
CCMPR02045000    saveDesign crashing
CCMPR02044921    ERROR: (IMPEXT-4021): Aborting read_parasitics due to previous errors...
CCMPR02044918    Innovus should skip any IO cell when collecting domain tech site
CCMPR02044791    Wire edit commands add redundant floating VIA10
CCMPR02044570    specifyBlackBot -cell crash
CCMPR02044541    -optimizeFF true for Hold is degrading DRV on both data and clock
CCMPR02044511    place_opt_design producing random result on rerun
CCMPR02043896    diagonal compaction not taking place fully as seen in this testcase
CCMPR02043881    Crash and DIAG Assert "peIsDesignExtracted() && peiExtStatus" after tQuantus RC extraction
CCMPR02043373    CTE slow run time
CCMPR02043363    Map  _noapplycpfrule option in CUI and make it public to add_power_switch both in CUI and Legacy
CCMPR02043297    Crash during saveDesign
CCMPR02043278    Connections with stackViaRule are not DRC clean
CCMPR02043269    ecoAddRepeater missing detail warning message if using -net versus -term
CCMPR02043233    Why top critical net is not layer assigned at place_opt compared to clock
CCMPR02043217    ccopt_design removing pre-routed routing
CCMPR02043109    SEGV while saving OA design after Cts (Stylus
CCMPR02043082    push partition_push_network is too slow with power_intent
CCMPR02042675    Cannot saveDesign due to DIAG in dbTerm.c getExtraRef with oaDB
CCMPR02042583    ecoRoute crashing when after restoreDesign -noTiming
CCMPR02042084    update_names is corrupting UPF
CCMPR02042083    CTS changes hnet name regardless of dont_touch
CCMPR02041883    Large # of DRCs on lower layers due to incorrect trim grid generation when placement blkg is present on bottom row
CCMPR02041870    ccopt_design -cts crash
CCMPR02041798    write_power_intent -1801 is taking longer than expected to dump out upf
CCMPR02041649    Placer needs to align placement of insts with M3 via pillars wrt M3 PG
CCMPR02040999    Module function not preserved after place_opt_design -opt
CCMPR02040993    **ERROR: (IMPESI-3201): Delay calculation failed for net .... and causing segv
CCMPR02040333    Power grid insertion to support RIGHTWAYONGRIDONLY EXCEPTWIDTH
CCMPR02040291    legalresize transform behavior is different for two versions lef files
CCMPR02040212    legalizePin issues IMPPTN-562 warning with strange coordinates
CCMPR02040038    IQRC does not see physical connectivity between terminal wire segment (IMPEXT-1392)
CCMPR02039644    routeDesign crash with setNanoRouteMode -routeWithTimingDriven true
CCMPR02039490    optDesign -postRoute -setup -hold isnot fixing all possible hold violations
CCMPR02039141    editPowerVia command to add power vias from M3 to M1 rails takes long time to complete
CCMPR02039116    Incorrect cell master coloring and instance flipping in placement
CCMPR02039110    Incorrect pin access locations on nearby pins to yield cut color violations
CCMPR02039084    ColorizePowerMesh hangs for long time
CCMPR02039062    NR leaves many open nets when access macro pin in FB1 region
CCMPR02039044    optDesign -postCTS w/ ILM got SEGV
CCMPR02039016    Via pillar related DRC violation when cell placed vertical abutment with required via pillars
CCMPR02038945    CCOpt is creating an inversion in the jtag clock tree, during "Optimizing outlier paths"
CCMPR02038882    Missing power domain coordinates after restoreDesign for nested power domain
CCMPR02038656    Tool crashing by fixVia -minStep command
CCMPR02038325    refinePlace issued lots of warnings: IMPSP-2042 and IMPSP-2031
CCMPR02038227    Filler node is crashing while executing the verifyLitho command
CCMPR02037777    CCOpt stops by ERROR (IMPCCOPT-1135)
CCMPR02037672    addRepeaterByRule crashes after using "free_power_intent"
CCMPR02037622    False via array spacing violations from check_drc
CCMPR02037582    synthesize_ccopt_flexible_htrees hangs at "Computing placement data for flexible H-tree"
CCMPR02037249    Placement crash issue after "place SDP groups
CCMPR02036952    Re-generate .apa file automatically if moved or deleted in the previous DB
CCMPR02036951    Hold TNS degrades with e050 after post-cts setup compared to e016
CCMPR02036922    globalDetailRoute -selected SEGV with 18.71-e173
CCMPR02036862    Please map legacy setViaGenMode -ignore_design_boundary to Stylus
CCMPR02036850    Long runtime of partition command
CCMPR02036828    NanoRoute crash 18.11, critical design
CCMPR02036805    Crash during the defIn command
CCMPR02036535    tQuantus TCAP/XCAP optimism Vs iQuantus in 18.12
CCMPR02036415    The PG modeling for stdcell placement is too pessimistic
CCMPR02036348    Nanoroute passive mode is not adhering to trim grid
CCMPR02036339    Power getting worse when include new mixed-driving-strength MBFF lib
CCMPR02036318    postcts SEGVs with cdcc14CompressedWave5reset
CCMPR02036306    -min_gap, -gap support in placement for safety islands
CCMPR02035635    Skew degradation after "Wire Capacitance"
CCMPR02035621    Crash in place_opt_desing during timing update
CCMPR02035579    Text box size from OA design become very large in Innovus
CCMPR02035562    Secondary PG opens after secondary PG route using addStripe
CCMPR02035281    Request to enhance S20 std cell pin access routing
CCMPR02035102    addFiller creates edge spacing violations
CCMPR02034883    Stacked vias not added when THICK_CU_D with is between 2.0 and 2.1
CCMPR02034653    Filler insertion on placed db leaves gaps and checkPlace DRCs after filler cell insertion
CCMPR02034641    addFiller with vert stack repair cell defined runs for over 60 hours
CCMPR02034562    assignPtnPin -forceAbutmentWithFixed true does not ignore standard cell abutment
CCMPR02034353    Powerplan via gen needs to support new CUTCLASS orientation syntax
CCMPR02034095    High fanout net connected to power switch cells is not getting buffered
CCMPR02034073    ISO cell placement issue
CCMPR02034052    Getting SEGV during read_sai when reading the constraint file
CCMPR02033663    Vague errors on reading the same CPF after free_power_intent
CCMPR02033345    DR violations grow by 5x after antenna fix diode insertion
CCMPR02033327    place_opt_design hang with Invs 18.12 & 18.13
CCMPR02033107    Non-determinism in FDS
CCMPR02032826    Need routing halo to behave as a hard constraint and apply to stdcells as well
CCMPR02032786    Crash with clock reporting command
CCMPR02032364    tQuantus vs signoff_Quantus is not good
CCMPR02031913    postRoute optDesign makes lots of fixable color violations
CCMPR02031696    Error IMPVB-23 while loading file in Innovus
CCMPR02031509    IR Aware refinePlace needs separate control for top and bottom padding
CCMPR02031489    Tool is crashing during the detailRoute -fix_drc in the filler node step
CCMPR02031404    Utilization not competitive
CCMPR02031059    Negative virtual delays after ECF
CCMPR02030247    Unacceptable runTime degradation (30X!) with path groups
CCMPR02028928    Crash during opt_design -post_route
CCMPR02028657    Jogs reported on NDR net
CCMPR02028415    Enhance write_lef_abstract to create minimum spacing cut out for non-rectangular pin
CCMPR02027131    HTREE synthesis hangs more than 2 days with DIAG message
CCMPR02026581    For Design having ilm create_clock_tree_spec generates 56ns early-tapping on 1 ilm reg clk pin
CCMPR02026556    Opens while connecting mustjoin pins
CCMPR02026480    synthesize_ccopt_flexible_htrees runs out of memory at "Computing placement data ..."
CCMPR02026253    Filler cell vertical stack issue
CCMPR02025887    Command reportCapViolation -all -min is not detecting min cap violation on port
CCMPR02025054    Via blockage and checker function enhancement
CCMPR02024562    addTieHiLow cannot add appropriate tie cell for its power domain
CCMPR02024309    NR adds via pillars on M0 pins causes M1 finger short with other cells' M1 pins or obs
CCMPR02024132    Clock routing creates stubs on few nets causing EM violations
CCMPR02023492    NDR violations on M5(6) for via_pillar
CCMPR02023456    Crash in msvConnectAlwaysOnPowerGround during place_opt_design in 17.71-e244
CCMPR02023431    Fill1 gap between MBFF and tap cells
CCMPR02022504    Insertion delay due to suboptimal tap assignment
CCMPR02022261    Hier Flow - assembleDesign writing out extra empty PG ports in instantiation
CCMPR02021331    optDesign -postRoute overlooks max_tran violation net
CCMPR02021083    Vias to mustjoin pins added with DRCs to PG
CCMPR02020880    verify_drc flags false NUT wire and via violations on all power routing
CCMPR02018941    CCOpt flexible h-tree drivers placed too close to each other (not honoring cell padding)
CCMPR02018290    Enhancement to allow for multiple FORBIDDENSPACING rules per CUTCLASS
CCMPR02018117    Extra vias appear after partition
CCMPR02017717    write_db crash seen in 18.12-e072 and 18.12-e080
CCMPR02017697    CCOpt stuck at netlist update
CCMPR02017582    Partition creates. fp file with <NULL> pgPin
CCMPR02017530    Long secondary P/G routing  to lower layer target while shorter target exist in higher metal
CCMPR02016957    SEGV during clock implementation routing
CCMPR02016716    ecoRoute fails because of nonexistent segment in PASS layer
CCMPR02016517    Lack of DRV fixing on N7 top level with INVS 18.11 (unexpected behavior of spGetBoxDemandAndSupply)
CCMPR02015629    Reduce m1 usage to create more locations for PG insertion
CCMPR02012390    Customer wants innovus to achieve ~179mW of total power Vs current ~200mW
CCMPR02011016    Default power domain gets partition box and not boxes
CCMPR02011003    Innovus v18.10-p002_1 NRHF - route quality for routing with single net length match constraint
CCMPR02009061    add_stripes is creating EolExt Spacing DRC violations
CCMPR02006567    False litho halo violations seen by NanoRoute, 18.11
CCMPR02004738    Crash during postroute power optimization
CCMPR02004533    To allow customized append prefix to auto generated vias (generateVias)
CCMPR02003347    route_eco/route_eco -fix_drc leaving 20-30 M1 trim2trim spacing violation in 18.12 builds
CCMPR02002052    Improve reporting to flag GDCAP cells inserted in the wrong power domain
CCMPR01993072    ib_cell does not honor padding
CCMPR01988532     Crash during timer update in cdcc::CompressedWave::updateWave using 18.12e033
CCMPR01985916    Miscorrelation between postRoute and preRoute extraction with leaf net caps
CCMPR01974522    write_lef_library creates invalid LEF file on cells with MUSTJOIN pins
CCMPR01969990    Use of Inverted ICG during cts
CCMPR01969151    Huge timing difference reported after running extractRc followed with report_timing in innovus
CCMPR01965080    report_ccopt_cell_halo_violations should output violation report for Violation Browser
CCMPR01955900    ECF flow development
CCMPR01952897    addFiller results in M1 spacing violations with signal routes
CCMPR01952514    Support regrouping master clone partitions inside non-unique modules
CCMPR01949092    18.20: DIAG [spiInitNewCellForPinMaskAlign] Attempt to color cell failed
CCMPR01948883    Budgeting missed to create a valid timing condition and missed set_analysis_view options
CCMPR01948207    Partitioning is wrongly removing rows at the top-level/inside partitions
CCMPR01928397    addRoutingHalo fail for PAD
CCMPR01921566    Innovus is not able to resolve cutSameMaskSpacing violations
CCMPR01914599    171/181 tool add AO cell which are not needed, such cell impact negatively frequency target
CCMPR01911530    Patchwires getting added create DRC violations. Patchwires not needed.
CCMPR01889342    verifyPowerVia command is flagging missing vias where cell blockage located
CCMPR01875721    18.1 big die area design optDesignDRV long runtime
CCMPR01859285    Stacktrace during writing timing model
CCMPR01817952    read_stream should also support oasis format
CCMPR01807374    verify_drc miss DRCs to diagonal special route
CCMPR01792686    custom_shape polygon is not being saved in common_ui and even object attribute is not working on it
CCMPR01731573    RefinePlace attempts to place AREA IOs
CCMPR01714367    Request way to remove custom layers from the Custom Layer tab of Color Preferences GUI