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For the non-intrusive ARM SVF, we need to delve more into the ARM chip (Zynq 7000 series) how we can better exploit the on-chip debugging facilities, the Performance Monitor Counters, Embedded Trace Macrocells Cross Triggers, and especially the CoreSight tracing and routing, compression and pipeline mechanisms, as far as possible for real time exploitation. Experience and knowledge in that domain is a major asset.


• ARM IO and bus model simulation: we need more information and study concerning the more demanding IO models, their generated memory traffic and their impact on the processor core performances as to be able to model them more accurately. Development of software based simulation models is needed to check accuracy.


• In the eARM project, we use the https://en.wikipedia.org/wiki/Tiny_C_Compiler , mainly for its performance in creating quickly compiled images. We need to investigate other possible solutions as to ensure potential speed improvements. We are thinking on more efficient ways of source code formulation, compiler improvements, definition of a local ABI and https://en.wikipedia.org/wiki/Calling_convention in order to better exploit modern CPU’s registers and instruction sets. We would like to investigate the extension of the used compiler to generate ARMV8 object code.



• For our HiL test systems on Zynq SoC’s, we would like to investigate the integration of an existing CCSDS/ECSS compatible Telemetry/Telecommand decoder IP such as on https://m.esa.int/Our_Activities/Space_Engineering_Technology/Microelectronics/PDEC and https://m.esa.int/Our_Activities/Space_Engineering_Technology/Microelectronics/PTME but again with extended as to support the PTP Timestamping Unit as to have a precise view on the timing so that we can make precise correlation with other events in the system


• Machine learning of execution traces of ARM programs. Modern SoC’s have many variations in clock, bus and cache settings and memory types, so it becomes quite difficult to validate if performance and time is nominal. Machine learning should help to validate real and simulated behaviour, while in the end allow to extract the critical parameters that define the system timing signature, such as memory read, write, fetch latencies, cache average timings, etc. It might be possible to learn the performance impact of one core to the others.