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  1. Index: lcd-fuzeplus.c
  2. ===================================================================
  3. --- lcd-fuzeplus.c      (revision 30931)
  4. +++ lcd-fuzeplus.c      (working copy)
  5. @@ -304,37 +304,37 @@
  6.  static void lcd_init_seq_9325(void)
  7.  {
  8.      _begin_seq()
  9. -    _lcd_write_reg(0xe5, 0x78f0)
  10. -    _lcd_write_reg(0xe3, 0x3008)
  11. -    _lcd_write_reg(0xe7, 0x12)
  12. -    _lcd_write_reg(0xef, 0x1231)
  13. -    _lcd_write_reg(0, 1)
  14. -    _lcd_write_reg(1, 0x100)
  15. -    _lcd_write_reg(2, 0x700)
  16. -    _lcd_write_reg(3, 0x1030)
  17. -    _lcd_write_reg(4, 0)
  18. -    _lcd_write_reg(8, 0x207)
  19. -    _lcd_write_reg(9, 0)
  20. -    _lcd_write_reg(0xa, 0)
  21. -    _lcd_write_reg(0xc, 0)
  22. -    _lcd_write_reg(0xd, 0)
  23. -    _lcd_write_reg(0xf, 0)
  24. -    _lcd_write_reg(0x10, 0)
  25. -    _lcd_write_reg(0x11, 7)
  26. -    _lcd_write_reg(0x12, 0)
  27. -    _lcd_write_reg(0x13, 0)
  28. +    _lcd_write_reg(0xe5, 0x78f0)  // ??? undocumented register
  29. +    _lcd_write_reg(0xe3, 0x3008)  // ??? undocumented register
  30. +    _lcd_write_reg(0xe7, 0x12)    // ??? undocumented register
  31. +    _lcd_write_reg(0xef, 0x1231)  // ??? undocumented register
  32. +    _lcd_write_reg(0, 1)          // Start Oscillation (R00h) [P53] | Turn display on
  33. +    _lcd_write_reg(1, 0x100)      // Driver Output Control Register (R01h) [P53] | SS=1 (shift direction of outputs is from S720 to S1)
  34. +    _lcd_write_reg(2, 0x700)      // LCD Driving Waveform Control (R02h) [P55] | Line inversion on
  35. +    _lcd_write_reg(3, 0x1030)     // Entry Mode (R03h) [P55] | AM=0; I/D=11 (horizontal and vertical increment); BGR=1 (Swap the RGB data to BGR in writing into GRAM)
  36. +    _lcd_write_reg(4, 0)          // Resizing Control Register (R04h) [P57] | No resizing
  37. +    _lcd_write_reg(8, 0x207)      // Display Control 2 (R08h) [P59] | Number of lines for Back Porch: 7 lines; Number of lines for Front Porch: 2 lines
  38. +    _lcd_write_reg(9, 0)          // Display Control 3 (R09h) [P60] | Scan Cycle: 0 frame
  39. +    _lcd_write_reg(0xa, 0)        // Display Control 4 (R0Ah) [P61] | Output Interval: 1 frame
  40. +    _lcd_write_reg(0xc, 0)        // RGB Display Interface Control 1 (R0Ch) [P62]
  41. +    _lcd_write_reg(0xd, 0)        // Frame Marker Position (R0Dh) [P63]
  42. +    _lcd_write_reg(0xf, 0)        // RGB Display Interface Control 2 (R0Fh) [P63]
  43. +    _lcd_write_reg(0x10, 0)       // Power Control 1 (R10h) [P64]
  44. +    _lcd_write_reg(0x11, 7)       // Power Control 2 (R11h) [P65] | VC=111 (ratio factor of Vci to generate the reference voltages Vci1: 1.0 x Vci)
  45. +    _lcd_write_reg(0x12, 0)       // Power Control 3 (R12h) [P66]
  46. +    _lcd_write_reg(0x13, 0)       // Power Control 4 (R13h) [P66]
  47.      _mdelay(20)
  48. -    _lcd_write_reg(0x10, 0x1290)
  49. -    _lcd_write_reg(0x11, 7)
  50. +    _lcd_write_reg(0x10, 0x1290)  // Power Control 1 (R10h) [P64] | AP=001 (Gamma driver amplifiers: 1.00, Source driver amplifiers: 1.00); APE=1 (start the generation of power supply); SAP=1 (Source driver is enabled); BT=010 (DDVDH: Vci1 x 2; VCL: - Vci1; VGH: Vci1 x 6; VGL: - Vci1 x 3)
  51. +    _lcd_write_reg(0x11, 7)       // Power Control 2 (R11h) [P65] | VC=111 (Vci1 voltage: 1.0 x Vci)
  52.      _mdelay(50)
  53. -    _lcd_write_reg(0x12, 0x19)
  54. +    _lcd_write_reg(0x12, 0x19)    // Power Control 3 (R12h) [P66] | PON=1 (VGL output is enabled); VRH=1001 (VREG1OUT: Vci x 1.65)
  55.      _mdelay(50)
  56. -    _lcd_write_reg(0x13, 0x1700)
  57. -    _lcd_write_reg(0x29, 0x14)
  58. +    _lcd_write_reg(0x13, 0x1700)  // Power Control 4 (R13h) [P66] | VDV=10111 (VCOM amplitude = VREG1OUT x 1.08)
  59. +    _lcd_write_reg(0x29, 0x14)    // Power Control 7 (R29h) [P69] | VCM=010100 (VCOMH voltage = VREG1OUT x 0.785)
  60.      _mdelay(50)
  61. -    _lcd_write_reg(0x20, 0)
  62. +    _lcd_write_reg(0x20, 0)       // GRAM Horizontal/Vertical Address Set (R20h, R21h) [P67]
  63.      _lcd_write_reg(0x21, 0)
  64. -    _lcd_write_reg(0x30, 0x504)
  65. +    _lcd_write_reg(0x30, 0x504)   // Gamma Control (R30h ~ R3Dh) [P71]
  66.      _lcd_write_reg(0x31, 7)
  67.      _lcd_write_reg(0x32, 6)
  68.      _lcd_write_reg(0x35, 0x106)
  69. @@ -344,23 +344,23 @@
  70.      _lcd_write_reg(0x39, 0x706)
  71.      _lcd_write_reg(0x3c, 0x204)
  72.      _lcd_write_reg(0x3d, 0x202)
  73. -    _lcd_write_reg(0x50, 0)
  74. +    _lcd_write_reg(0x50, 0)       // Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) [P71]
  75.      _lcd_write_reg(0x51, 0xef)
  76.      _lcd_write_reg(0x52, 0)
  77.      _lcd_write_reg(0x53, 0x13f)
  78. -    _lcd_write_reg(0x60, 0xa700)
  79. +    _lcd_write_reg(0x60, 0xa700)  // Gate Scan Control (R60h, R61h, R6Ah) [P72]
  80.      _lcd_write_reg(0x61, 1)
  81.      _lcd_write_reg(0x6a, 0)
  82. -    _lcd_write_reg(0x2b, 0xd)
  83. +    _lcd_write_reg(0x2b, 0xd)     // Frame Rate and Color Control (R2Bh) [P70] | FRS=1101 (Frame Rate: 128)
  84.      _mdelay(50)
  85. -    _lcd_write_reg(0x90, 0x11)
  86. -    _lcd_write_reg(0x92, 0x600)
  87. -    _lcd_write_reg(0x93, 3)
  88. -    _lcd_write_reg(0x95, 0x110)
  89. -    _lcd_write_reg(0x97, 0)
  90. -    _lcd_write_reg(0x98, 0)
  91. -    _lcd_write_reg(7, 0x173)
  92. -    _lcd_write_reg(0x22, 0)
  93. +    _lcd_write_reg(0x90, 0x11)    // Panel Interface Control 1 (R90h) [P75] | RTNI=10001 (Clocks/Line: 17 clocks)
  94. +    _lcd_write_reg(0x92, 0x600)   // Panel Interface Control 2 (R92h) [P76] | NOWI=110 (Gate Non-overlap Period: 6 clocks)
  95. +    _lcd_write_reg(0x93, 3)       // ??? undocumented register
  96. +    _lcd_write_reg(0x95, 0x110)   // Panel Interface Control 4 (R95h) [P76] | RTNE=010000 (Clocks per line period: 16 clocks); DIVE=01 (division ratio of DOTCLK: 1/4)
  97. +    _lcd_write_reg(0x97, 0)       // ??? undocumented register
  98. +    _lcd_write_reg(0x98, 0)       // ??? undocumented register
  99. +    _lcd_write_reg(7, 0x173)      // Display Control 1 (R07h) [P58] | D=11 (turn on the display panel); CL=0 (Colors: 262,144); GON+DTE=11 (G1 ~G320 Gate Output: Normal Display); UNKNOWN=1 (????); BASEE=1 (the base image is displayed)
  100. +    _lcd_write_reg(0x22, 0)       // Write Data to GRAM (R22h) [P67]
  101.      _end_seq()
  102.  }
  103.  
  104. @@ -427,38 +427,38 @@
  105.      if(!enable)
  106.      {
  107.          _begin_seq()
  108. -        _lcd_write_reg(7, 0x131)
  109. +        _lcd_write_reg(7, 0x131)    // Display Control 1 (R07h) [P58] | D=01 (turn off the display panel, retain graphics); CL=0 (Colors: 262,144); GON+DTE=11 (G1 ~G320 Gate Output: Normal Display); BASEE=1 (the base image is displayed)
  110.          _mdelay(10)
  111. -        _lcd_write_reg(7, 0x130)
  112. +        _lcd_write_reg(7, 0x130)    // Display Control 1 (R07h) [P58] | D=00 (turn off and halt the display panel); CL=0 (Colors: 262,144); GON+DTE=11 (G1 ~G320 Gate Output: Normal Display); BASEE=1 (the base image is displayed)
  113.          _mdelay(10)
  114. -        _lcd_write_reg(7, 0)
  115. -        _lcd_write_reg(0x10, 0x80)
  116. -        _lcd_write_reg(0x11, 0)
  117. -        _lcd_write_reg(0x12, 0)
  118. -        _lcd_write_reg(0x13, 0)
  119. +        _lcd_write_reg(7, 0)        // Display Control 1 (R07h) [P58] | disable completely
  120. +        _lcd_write_reg(0x10, 0x80)  // Power Control 1 (R10h) [P64] | 10000000 | AP=000 (Gamma driver amplifiers: halt, Source driver amplifiers: halt); APE=1 (start the generation of power supply); SAP=0 (Source driver is disabled)
  121. +        _lcd_write_reg(0x11, 0)     // Power Control 2 (R11h) [P65]
  122. +        _lcd_write_reg(0x12, 0)     // Power Control 3 (R12h) [P66]
  123. +        _lcd_write_reg(0x13, 0)     // Power Control 4 (R13h) [P66]
  124.          _mdelay(200)
  125. -        _lcd_write_reg(0x10, 0x82)
  126. +        _lcd_write_reg(0x10, 0x82)  // Power Control 1 (R10h) [P64] | 10000010 | STB=1 (enters the standby mode); APE=1 (start the generation of power supply)
  127.          _end_seq()
  128.      }
  129.      else
  130.      {
  131.          _begin_seq()
  132. -        _lcd_write_reg(0x10, 0x80)
  133. -        _lcd_write_reg(0x11, 0)
  134. -        _lcd_write_reg(0x12, 0)
  135. -        _lcd_write_reg(0x13, 0)
  136. -        _lcd_write_reg(7, 1)
  137. +        _lcd_write_reg(0x10, 0x80)    // Power Control 1 (R10h) [P64] | 10000000 | AP=000 (Gamma driver amplifiers: halt, Source driver amplifiers: halt); APE=1 (start the generation of power supply); STB=0 (exit the standby mode);
  138. +        _lcd_write_reg(0x11, 0)       // Power Control 2 (R11h) [P65]
  139. +        _lcd_write_reg(0x12, 0)       // Power Control 3 (R12h) [P66]
  140. +        _lcd_write_reg(0x13, 0)       // Power Control 4 (R13h) [P66]
  141. +        _lcd_write_reg(7, 1)          // Display Control 1 (R07h) [P58] | enable display
  142.          _mdelay(200)
  143. -        _lcd_write_reg(0x10, 0x1290)
  144. -        _lcd_write_reg(0x11, 7)
  145. +        _lcd_write_reg(0x10, 0x1290)  // Power Control 1 (R10h) [P64] | AP=001 (Gamma driver amplifiers: 1.00, Source driver amplifiers: 1.00); APE=1 (start the generation of power supply); SAP=1 (Source driver is enabled); BT=010 (DDVDH: Vci1 x 2; VCL: - Vci1; VGH: Vci1 x 6; VGL: - Vci1 x 3)
  146. +        _lcd_write_reg(0x11, 7)       // Power Control 2 (R11h) [P65] | VC=111 (ratio factor of Vci to generate the reference voltages Vci1: 1.0 x Vci)
  147.          _mdelay(50)
  148. -        _lcd_write_reg(0x12, 0x19)
  149. +        _lcd_write_reg(0x12, 0x19)    // Power Control 3 (R12h) [P66] | PON=1 (VGL output is enabled); VRH=1001 (VREG1OUT: Vci x 1.65)
  150.          _mdelay(50)
  151. -        _lcd_write_reg(0x13, 0x1700)
  152. -        _lcd_write_reg(0x29, 0x10)
  153. +        _lcd_write_reg(0x13, 0x1700)  // Power Control 4 (R13h) [P66] | VDV=10111 (VCOM amplitude = VREG1OUT x 1.08)
  154. +        _lcd_write_reg(0x29, 0x10)    // Power Control 7 (R29h) [P69] | VCM=010000 (VCOMH voltage = VREG1OUT x 0.765)
  155.          _mdelay(50)
  156. -        _lcd_write_reg(7, 0x133)
  157. -        _lcd_write_reg(0x22, 0)
  158. +        _lcd_write_reg(7, 0x133)      // Display Control 1 (R07h) [P58] | 1 00 11 0 0 11 | D=11, BASEE=1 (Base image display, Operate); GON+DTE=11 (G1 ~G320 Gate Output: Normal Display)
  159. +        _lcd_write_reg(0x22, 0)       // Write Data to GRAM (R22h) [P67]
  160.          _end_seq()
  161.      }
  162.  }
  163.  
  164.  
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