diff --git a/sys/mips/atheros/apb.c b/sys/mips/atheros/apb.c
index c004741..f4ada18 100644
--- a/sys/mips/atheros/apb.c
+++ b/sys/mips/atheros/apb.c
@@ -345,6 +345,9 @@ apb_intr(void *arg)
                                continue;
                        }

+                       /* XXX - AR7240 hack - need to ack every interrupt */
+                       ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS, reg & ~(1 << irq));
+
                        /* TODO: frame instead of NULL? */
                        intr_event_handle(event, NULL);
                        mips_intrcnt_inc(sc->sc_intr_counter[irq]);
diff --git a/sys/mips/atheros/ar71xx_machdep.c b/sys/mips/atheros/ar71xx_machdep.c
index c8abc74..dd083e1 100644
--- a/sys/mips/atheros/ar71xx_machdep.c
+++ b/sys/mips/atheros/ar71xx_machdep.c
@@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
 #include <mips/sentry5/s5reg.h>

 #include "opt_ddb.h"
+#include "opt_athmips.h"

 #include <sys/param.h>
 #include <sys/conf.h>
@@ -147,6 +148,9 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused,
        int argc, i, count = 0;
        char **argv, **envp, *var;
        vm_offset_t kernend;
+#if defined(UBOOT_AR71XX_MACADDRESS) || defined(UBOOT_AR72XX_MACADDRESS)
+       char *mac;
+#endif

        /*
         * clear the BSS and SBSS segments, this should be first call in
@@ -254,6 +258,23 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused,
                freeenv(var);
        }

+#if defined(UBOOT_AR71XX_MACADDRESS)
+       printf("%s: reading if_arge mac address from 0x1f01fc00\n", __func__);
+       /* uboot hack for ar71xx! */
+       mac = (char *) MIPS_PHYS_TO_KSEG1(0x1f01fc00);
+       for (i = 0; i < 6; i++) {
+               ar711_base_mac[i] = mac[i];
+       }
+#endif
+#if defined(UBOOT_AR72XX_MACADDRESS)
+       printf("%s: reading if_arge mac address from 0x1fff0000\n", __func__);
+       /* uboot hack for ar724x! */
+       mac = (char *) MIPS_PHYS_TO_KSEG1(0x1fff0000);
+       for (i = 0; i < 6; i++) {
+               ar711_base_mac[i] = mac[i];
+       }
+#endif
+
        init_param2(physmem);
        mips_cpu_init();
        pmap_bootstrap();
diff --git a/sys/mips/atheros/ar724x_chip.c b/sys/mips/atheros/ar724x_chip.c
index 450dd19..136db96 100644
--- a/sys/mips/atheros/ar724x_chip.c
+++ b/sys/mips/atheros/ar724x_chip.c
@@ -126,21 +126,27 @@ ar724x_chip_device_stopped(uint32_t mask)
 static void
 ar724x_chip_set_pll_ge0(int speed)
 {
+
+printf("%s: called\n", __func__);
 }

 static void
 ar724x_chip_set_pll_ge1(int speed)
 {
+
+printf("%s: called\n", __func__);
 }

 static void
 ar724x_chip_ddr_flush_ge0(void)
 {
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 }

 static void
 ar724x_chip_ddr_flush_ge1(void)
 {
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 }

 static uint32_t
@@ -149,6 +155,29 @@ ar724x_chip_get_eth_pll(unsigned int mac, int speed)
         return 0;
 }

+static void
+ar724x_chip_init_usb_peripheral(void)
+{
+
+       printf("%s: FIXME!\n", __func__);
+#if 0
+        ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+        DELAY(1000);
+
+        ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+        DELAY(1000);
+
+        ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
+            USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
+            USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
+
+        ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
+            (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
+
+        DELAY(1000);
+#endif
+}
+
 struct ar71xx_cpu_def ar724x_chip_def = {
         &ar724x_chip_detect_mem_size,
         &ar724x_chip_detect_sys_frequency,
@@ -161,5 +190,5 @@ struct ar71xx_cpu_def ar724x_chip_def = {
         &ar724x_chip_ddr_flush_ge1,
         &ar724x_chip_get_eth_pll,
        NULL,           /* ar71xx_chip_irq_flush_ip2 */
-       NULL            /* ar71xx_chip_init_usb_peripheral */
+       &ar724x_chip_init_usb_peripheral,
 };
diff --git a/sys/mips/atheros/ar724xreg.h b/sys/mips/atheros/ar724xreg.h
index ec7ef15..ad3fa78 100644
--- a/sys/mips/atheros/ar724xreg.h
+++ b/sys/mips/atheros/ar724xreg.h
@@ -47,6 +47,9 @@

 #define        AR724X_BASE_FREQ                5000000

+#define        AR724X_DDR_REG_FLUSH_GE0        (AR71XX_DDR_CONFIG + 0x7c)
+#define        AR724X_DDR_REG_FLUSH_GE1        (AR71XX_DDR_CONFIG + 0x80)
+
 #define        AR724X_RESET_REG_RESET_MODULE   AR71XX_RST_BLOCK_BASE + 0x1c
 #define        AR724X_RESET_MODULE_USB_OHCI_DLL        (1 << 3)