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- .cpu arm946e-s
- .arch armv5te
- .section .text.start
- file_name:
- .STRING16 "/test.bin"
- .global _start
- .arm
- .align 2
- _start:
- ldr sp, =0x20100000
- ldr r0, =gain_control
- svc 0x7B
- adr r0, file_name
- bl open9
- b main
- gain_control:
- STMFD SP!, {R0-R10,LR}
- ldr r0, =0x10000035
- mcr p15, 0, r0, c6, c3, 0
- mrc p15, 0, r0, c2, c0, 0
- mrc p15, 0, r12, c2, c0, 1
- mrc p15, 0, r1, c3, c0, 0
- mrc p15, 0, r2, c5, c0, 2
- mrc p15, 0, r3, c5, c0, 3
- and r2, r2 , #0xfff0ffff
- and r3, r3 , #0xfff0ffff
- ldr r4, =0x33333333
- mov r2, r4
- mov r3, r4
- orr r0, r0 , #0x00000010
- orr r12, r12, #0x00000010
- orr r1, r1 , #0x00000010
- mcr p15, 0, r0, c2, c0, 0
- mcr p15, 0, r12, c2, c0, 1
- mcr p15, 0, r1, c3, c0, 0
- mcr p15, 0, r2, c5, c0, 2
- mcr p15, 0, r3, c5, c0, 3
- ldr r0, =0x18000035
- mcr p15, 0, r0, c6, c4, 0
- mrc p15, 0, r0, c2, c0, 0
- mrc p15, 0, r1, c2, c0, 1
- mrc p15, 0, r2, c3, c0, 0
- orr r0, r0 , #0x20
- orr r1, r1, #0x20
- orr r2, r2 , #0x20
- mcr p15, 0, r0, c2, c0, 0
- mcr p15, 0, r1, c2, c0, 1
- mcr p15, 0, r2, c3, c0, 0
- LDMFD SP!, {R0-R10,PC}
- open9:
- STMFD SP!, {R4-R10,LR}
- SUB SP, SP, #0x30
- ADD r7, r0, #0
- LDR R5, =0x809797C
- LDR R5, [R5]
- ADD R5, #8
- LDR R1, =0x2EA0
- ADD R0, R5, R1
- ADD R1, SP, #8
- LDR R4, =0x8061451
- BLX R4
- MOV R3, #0
- STR R3, [SP,#0x1C]
- STR R3, [SP]
- STR R3, [SP,#4]
- ADD R0, SP, #0x10
- MOV R1, R5
- LDR R2, [SP,#8]
- LDR R3, [SP,#0xC]
- LDR R4, =0x8063F91
- BLX R4
- LDR R6, [SP,#0x1C]
- ADD R0, SP, #0x24
- MOV R1, #4
- STR R1, [R0]
- MOV R1, #0x1C
- STR R1, [R0,#8]
- ADD r1, r7, #0
- STR R1, [R0,#4]
- MOV R0, #0
- STR R0, [SP, #0x20]
- MOV R3, #7
- STR R3, [SP]
- STR R0, [SP,#4]
- ADD R1, SP, #0x20
- MOV R2, #0
- ADD R3, SP, #0x24
- LDR R10, =0x8084739
- MOV R0, R6
- #BLX R10
- LDR R0, [SP, #0x20]
- ADD SP, SP, #0x30
- LDMFD SP!, {R4-R10,PC}
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