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- module testModule2(
- input iCLK,
- output reg oSig
- );
- reg [23 :0] rCnt;
- always @( posedge iCLK ) rCnt = rCnt + 1;
- if (rCnt[22]) rCnt = 24'hFFFFF
- always oSig = rCnt[22];
- endmodule
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