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- ==========================================================================
- == Memory bandwidth tests ==
- == ==
- == Note 1: 1MB = 1000000 bytes ==
- == Note 2: Results for 'copy' tests show how many bytes can be ==
- == copied per second (adding together read and writen ==
- == bytes would have provided twice higher numbers) ==
- == Note 3: 2-pass copy means that we are using a small temporary buffer ==
- == to first fetch data into it, and only then write it to the ==
- == destination (source -> L1 cache, L1 cache -> destination) ==
- == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
- == brackets ==
- ==========================================================================
- C copy backwards : 1843.0 MB/s (1.3%)
- C copy backwards (32 byte blocks) : 1868.9 MB/s (1.0%)
- C copy backwards (64 byte blocks) : 1868.2 MB/s (1.2%)
- C copy : 1928.6 MB/s (1.9%)
- C copy prefetched (32 bytes step) : 1392.3 MB/s
- C copy prefetched (64 bytes step) : 1578.1 MB/s
- C 2-pass copy : 1560.4 MB/s
- C 2-pass copy prefetched (32 bytes step) : 1127.0 MB/s
- C 2-pass copy prefetched (64 bytes step) : 1038.1 MB/s
- C fill : 8302.7 MB/s (0.1%)
- C fill (shuffle within 16 byte blocks) : 8302.9 MB/s (0.1%)
- C fill (shuffle within 32 byte blocks) : 8309.9 MB/s (0.2%)
- C fill (shuffle within 64 byte blocks) : 8309.7 MB/s (0.2%)
- ---
- standard memcpy : 1933.9 MB/s
- standard memset : 8317.6 MB/s
- ---
- NEON LDP/STP copy : 1972.5 MB/s (0.4%)
- NEON LDP/STP copy pldl2strm (32 bytes step) : 1293.9 MB/s (1.5%)
- NEON LDP/STP copy pldl2strm (64 bytes step) : 1638.0 MB/s (0.2%)
- NEON LDP/STP copy pldl1keep (32 bytes step) : 2189.1 MB/s
- NEON LDP/STP copy pldl1keep (64 bytes step) : 2192.9 MB/s
- NEON LD1/ST1 copy : 1966.4 MB/s (0.2%)
- NEON STP fill : 8322.4 MB/s (0.1%)
- ARM LDP/STP copy : 1975.5 MB/s (0.2%)
- ARM STP fill : 8322.2 MB/s (0.1%)
- ARM STNP fill : 2874.0 MB/s (1.2%)
- ==========================================================================
- == Memory latency test ==
- == ==
- == Average time is measured for random memory accesses in the buffers ==
- == of different sizes. The larger is the buffer, the more significant ==
- == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
- == accesses. For extremely large buffer sizes we are expecting to see ==
- == page table walk with several requests to SDRAM for almost every ==
- == memory access (though 64MiB is not nearly large enough to experience ==
- == this effect to its fullest). ==
- == ==
- == Note 1: All the numbers are representing extra time, which needs to ==
- == be added to L1 cache latency. The cycle timings for L1 cache ==
- == latency can be usually found in the processor documentation. ==
- == Note 2: Dual random read means that we are simultaneously performing ==
- == two independent memory accesses at a time. In the case if ==
- == the memory subsystem can't handle multiple outstanding ==
- == requests, dual random read has the same timings as two ==
- == single reads performed one after another. ==
- ==========================================================================
- block size : single random read / dual random read
- 1024 : 0.0 ns / 0.0 ns
- 2048 : 0.0 ns / 0.0 ns
- 4096 : 0.0 ns / 0.0 ns
- 8192 : 0.0 ns / 0.0 ns
- 16384 : 0.0 ns / 0.0 ns
- 32768 : 0.0 ns / 0.0 ns
- 65536 : 4.8 ns / 8.0 ns
- 131072 : 7.4 ns / 11.6 ns
- 262144 : 8.7 ns / 12.2 ns
- 524288 : 9.6 ns / 12.9 ns
- 1048576 : 79.9 ns / 123.6 ns
- 2097152 : 118.0 ns / 160.2 ns
- 4194304 : 143.3 ns / 180.6 ns
- 8388608 : 156.4 ns / 190.3 ns
- 16777216 : 164.2 ns / 197.1 ns
- 33554432 : 169.4 ns / 201.5 ns
- 67108864 : 173.3 ns / 204.1 ns
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