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  1.  
  2. ==========================================================================
  3. == Memory bandwidth tests ==
  4. == ==
  5. == Note 1: 1MB = 1000000 bytes ==
  6. == Note 2: Results for 'copy' tests show how many bytes can be ==
  7. == copied per second (adding together read and writen ==
  8. == bytes would have provided twice higher numbers) ==
  9. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  10. == to first fetch data into it, and only then write it to the ==
  11. == destination (source -> L1 cache, L1 cache -> destination) ==
  12. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  13. == brackets ==
  14. ==========================================================================
  15.  
  16. C copy backwards : 1843.0 MB/s (1.3%)
  17. C copy backwards (32 byte blocks) : 1868.9 MB/s (1.0%)
  18. C copy backwards (64 byte blocks) : 1868.2 MB/s (1.2%)
  19. C copy : 1928.6 MB/s (1.9%)
  20. C copy prefetched (32 bytes step) : 1392.3 MB/s
  21. C copy prefetched (64 bytes step) : 1578.1 MB/s
  22. C 2-pass copy : 1560.4 MB/s
  23. C 2-pass copy prefetched (32 bytes step) : 1127.0 MB/s
  24. C 2-pass copy prefetched (64 bytes step) : 1038.1 MB/s
  25. C fill : 8302.7 MB/s (0.1%)
  26. C fill (shuffle within 16 byte blocks) : 8302.9 MB/s (0.1%)
  27. C fill (shuffle within 32 byte blocks) : 8309.9 MB/s (0.2%)
  28. C fill (shuffle within 64 byte blocks) : 8309.7 MB/s (0.2%)
  29. ---
  30. standard memcpy : 1933.9 MB/s
  31. standard memset : 8317.6 MB/s
  32. ---
  33. NEON LDP/STP copy : 1972.5 MB/s (0.4%)
  34. NEON LDP/STP copy pldl2strm (32 bytes step) : 1293.9 MB/s (1.5%)
  35. NEON LDP/STP copy pldl2strm (64 bytes step) : 1638.0 MB/s (0.2%)
  36. NEON LDP/STP copy pldl1keep (32 bytes step) : 2189.1 MB/s
  37. NEON LDP/STP copy pldl1keep (64 bytes step) : 2192.9 MB/s
  38. NEON LD1/ST1 copy : 1966.4 MB/s (0.2%)
  39. NEON STP fill : 8322.4 MB/s (0.1%)
  40. ARM LDP/STP copy : 1975.5 MB/s (0.2%)
  41. ARM STP fill : 8322.2 MB/s (0.1%)
  42. ARM STNP fill : 2874.0 MB/s (1.2%)
  43.  
  44. ==========================================================================
  45. == Memory latency test ==
  46. == ==
  47. == Average time is measured for random memory accesses in the buffers ==
  48. == of different sizes. The larger is the buffer, the more significant ==
  49. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  50. == accesses. For extremely large buffer sizes we are expecting to see ==
  51. == page table walk with several requests to SDRAM for almost every ==
  52. == memory access (though 64MiB is not nearly large enough to experience ==
  53. == this effect to its fullest). ==
  54. == ==
  55. == Note 1: All the numbers are representing extra time, which needs to ==
  56. == be added to L1 cache latency. The cycle timings for L1 cache ==
  57. == latency can be usually found in the processor documentation. ==
  58. == Note 2: Dual random read means that we are simultaneously performing ==
  59. == two independent memory accesses at a time. In the case if ==
  60. == the memory subsystem can't handle multiple outstanding ==
  61. == requests, dual random read has the same timings as two ==
  62. == single reads performed one after another. ==
  63. ==========================================================================
  64.  
  65. block size : single random read / dual random read
  66. 1024 : 0.0 ns / 0.0 ns
  67. 2048 : 0.0 ns / 0.0 ns
  68. 4096 : 0.0 ns / 0.0 ns
  69. 8192 : 0.0 ns / 0.0 ns
  70. 16384 : 0.0 ns / 0.0 ns
  71. 32768 : 0.0 ns / 0.0 ns
  72. 65536 : 4.8 ns / 8.0 ns
  73. 131072 : 7.4 ns / 11.6 ns
  74. 262144 : 8.7 ns / 12.2 ns
  75. 524288 : 9.6 ns / 12.9 ns
  76. 1048576 : 79.9 ns / 123.6 ns
  77. 2097152 : 118.0 ns / 160.2 ns
  78. 4194304 : 143.3 ns / 180.6 ns
  79. 8388608 : 156.4 ns / 190.3 ns
  80. 16777216 : 164.2 ns / 197.1 ns
  81. 33554432 : 169.4 ns / 201.5 ns
  82. 67108864 : 173.3 ns / 204.1 ns
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