CPU FIle

#bits 16

#subruledef REGS
{
	R0  => 0
	R1  => 1
	R2  => 2
	R3  => 3
	R4  => 4
	R5  => 5
	R6  => 6
	R7  => 7
	R8  => 8
	R9  => 9
	R10 => 10
	R11 => 11
	R12 => 12
	R13 => 13
	R14 => 14
	R15 => 15
	XH  => 10
	XL  => 11
	YH  => 12
	YL  => 13
	SPH => 14
	SPL => 15
}

#subruledef CON
{
	Z  => 0b0001
	C  => 0b0010
	N  => 0b0011
	R  => 0b0100
	NZ => 0b0101
	NC => 0b0110
	NN => 0b0111
}

#ruledef
{
	JR {VAL}									=> {REL = (VAL - pc), assert(REL <= 127 || REL >= -128), REL[7:0] @ 0b0000 @ 0[3:0]}
	JR {C:CON} {VAL}							=> {REL = (VAL - pc), assert(REL <= 127 || REL >= -128), REL[7:0] @ C[3:0] @ 0[3:0]}

	JMP {ADDR}									=> 0b000000000000 @ 14[3:0] @ ADDR[15:0]
	JMP {Rb:REGS}, {ADDR}						=> 0b0000 @ Rb[3:0] @ 0b0001 @ 14[3:0] @ ADDR[15:0]

	LD {Re:REGS}, ({ADDR})						=> 0b0000 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, (X)							=> 0b0001 @ Re[3:0] @ 0b0000 @ 1[3:0]
	LD {Re:REGS}, (Y)							=> 0b0010 @ Re[3:0] @ 0b0000 @ 1[3:0]
	LD {Re:REGS}, ({Rb:REGS}, {ADDR})			=> 0b0011 @ Re[3:0] @ Rb[3:0] @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, ({ADDR}, {Rb:REGS})			=> 0b0011 @ Re[3:0] @ Rb[3:0] @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, (X, {ADDR})					=> 0b0100 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, ({ADDR}, X)					=> 0b0100 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, (Y, {ADDR})					=> 0b0101 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, ({ADDR}, Y)					=> 0b0101 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD {Re:REGS}, (SP, {ADDR})					=> 0b0110 @ Re[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]

	LD ({ADDR}), {Ra:REGS}						=> 0b1000 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD (X), {Ra:REGS}							=> 0b1001 @ Ra[3:0] @ 0b0000 @ 1[3:0]
	LD (Y), {Ra:REGS}							=> 0b1010 @ Ra[3:0] @ 0b0000 @ 1[3:0]
	LD ({Rb:REGS}, {ADDR}), {Ra:REGS}			=> 0b1011 @ Ra[3:0] @ Rb[3:0] @ 1[3:0] @ ADDR[15:0]
	LD ({ADDR}, {Rb:REGS}), {Ra:REGS}			=> 0b1011 @ Ra[3:0] @ Rb[3:0] @ 1[3:0] @ ADDR[15:0]
	LD (X, {ADDR}), {Ra:REGS}					=> 0b1100 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD ({ADDR}, X), {Ra:REGS}					=> 0b1100 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD (Y, {ADDR}), {Ra:REGS}					=> 0b1101 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD ({ADDR}, Y), {Ra:REGS}					=> 0b1101 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]
	LD (SP, {ADDR}), {Ra:REGS}					=> 0b1110 @ Ra[3:0] @ 0b0000 @ 1[3:0] @ ADDR[15:0]

	LD {Re:REGS}, {VAL}							=> VAL[7:0] @ Re[3:0] @ 2[3:0]
	LD {Re:REGS}, {Ra:REGS}						=> 0b1111 @ Re[3:0] @ Ra[3:0] @ 3[3:0]

	LD {Re:REGS}, FL							=> 0b1110 @ Re[3:0] @ 0b0000 @ 3[3:0]
	LD FL, {Ra:REGS}							=> 0b1101 @ Ra[3:0] @ 0b0000 @ 3[3:0]

	ADD {Rae:REGS}, {Rb:REGS}					=> 0b0000 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	ADC {Rae:REGS}, {Rb:REGS}					=> 0b0001 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	SUB {Rae:REGS}, {Rb:REGS}					=> 0b0010 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	SBC {Rae:REGS}, {Rb:REGS}					=> 0b0011 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	AND {Rae:REGS}, {Rb:REGS}					=> 0b0100 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	OR {Rae:REGS}, {Rb:REGS}					=> 0b0101 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	XOR {Rae:REGS}, {Rb:REGS}					=> 0b0110 @ Rae[3:0] @ Rb[3:0] @ 3[3:0]
	CMP {Ra:REGS}, {Rb:REGS}					=> 0b0111 @ Ra[3:0] @ Rb[3:0] @ 3[3:0]
	INC {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0000 @ 3[3:0]
	ICC {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0001 @ 3[3:0]
	DEC {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0010 @ 3[3:0]
	DCC {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0011 @ 3[3:0]
	SFL {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0100 @ 3[3:0]
	SFR {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0101 @ 3[3:0]
	ROL {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0110 @ 3[3:0]
	ROR {Rae:REGS}								=> 0b1000 @ Rae[3:0] @ 0b0111 @ 3[3:0]

	ADD {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 4[3:0]
	ADC {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 5[3:0]
	SUB {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 6[3:0]
	SBC {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 7[3:0]
	AND {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 8[3:0]
	OR {Re:REGS}, {VAL}							=> VAL[7:0] @ Re[3:0] @ 9[3:0]
	XOR {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 10[3:0]
	CMP {Re:REGS}, {VAL}						=> VAL[7:0] @ Re[3:0] @ 11[3:0]

	IN {Re:REGS}, ({VAL})						=> VAL[7:0] @ Re[3:0] @ 12[3:0]
	OUT ({VAL}), {Ra:REGS}						=> VAL[7:0] @ Ra[3:0] @ 13[3:0]

	PUSH {Ra:REGS}								=> 0b0000 @ Ra[3:0] @ 0b0010 @ 14[3:0]
	POP {Re:REGS}								=> 0b0000 @ Re[3:0] @ 0b0011 @ 14[3:0]

	CALL {VAL}									=> {REL = (VAL - pc), assert(REL <= 127 && REL >= -128), REL[7:0] @ 0b0100 @ 14[3:0]}
	CALL {ADDR}									=> {REL = (ADDR - pc), assert(REL > 127 || REL < -128), 0b000000000101 @ 14[3:0] @ ADDR[15:0]}
	CALL {Rb:REGS}, {ADDR}						=> 0b0000 @ Rd[3:0] @ 0b0110 @ 14[3:0] @ ADDR[15:0]

	RET											=> 0b000000000000 @ 15[3:0]
	CLR Z										=> 0b000000000001 @ 15[3:0]
	SET Z										=> 0b000000000010 @ 15[3:0]
	CLR C										=> 0b000000000011 @ 15[3:0]
	SET C										=> 0b000000000100 @ 15[3:0]
	CLR N										=> 0b000000000101 @ 15[3:0]
	SET N										=> 0b000000000110 @ 15[3:0]
	CLR I										=> 0b000000000111 @ 15[3:0]
	SET I										=> 0b000000001000 @ 15[3:0]
	HALT										=> 0b1111111111111111
}