module RS_gates (
    input clk, R, S,
    output Q
    );

    (* KEEP = "TRUE" *) wire R_g, S_g, Qa, Qb;

    and (R_g, R, clk);
    and (S_g, S, clk);
    nor (Qa, R_g, Qb);
    nor (Qb, S_g, Qa);

    assign Q = Qa;
endmodule

//module Zadanie3 (
//  input [2:0] SW,
//  output [0:0] LEDR
//);
//
//  RS_gates ex (SW[2], SW[1], SW[0], LEDR[0]);
//
//endmodule


module RS_boolean (
    input Clk, R, S,
    output Q
    );

    (* KEEP = "TRUE" *) wire R_g, S_g, Qa, Qb;

    assign R_g = R & Clk;
    assign S_g = S & Clk;
    assign Qa = ~(R_g | Qb);
    assign Qb = ~(S_g | Qa);

    assign Q = Qa;
endmodule

//module Zadanie3 (
//  input [2:0] SW,
//  output [0:0] LEDR
//);
//
//  RS_boolean ex (SW[2], SW[1], SW[0], LEDR[0]);
//
//endmodule

module D_latch (
    input Clk, D,
    output Q
);

    (* KEEP = "TRUE" *) wire R_g, S_g, Qa, Qb;

    nand (S_g, D, Clk);
    nand (R_g, ~D, Clk);
    nand (Qa, S_g, Qb);
    nand (Qb, R_g, Qa);

    assign Q = Qa;

endmodule

module master_slave_D (
    input D, clk,
    output Q
);

    wire Qm;

    D_latch master (~clk, D, Qm);
    D_latch slave (clk, Qm, Q);

endmodule

//module Zadanie3 (
//  input [1:0] SW,
//  output [0:0] LEDR
//);
//
//  master_slave_D ex (SW[1], SW[0], LEDR[0]);
//
//endmodule

module latch_FDDP_FDDN (
    input D, clk,
    output Q
);

    wire Qa, Qb, Qc;

    D_latch ex0 (clk, D, Qa);
    D_latch ex1 (~clk, D, Qb);
    D_latch ex2 (~clk, D, Qc);

endmodule