`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    16:36:44 05/29/2014
// Design Name:
// Module Name:    up
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module up(input CLK, RST, X1,X2,
        output Z1, Z2, Z3, M,
        output [3:0] _PC,
        output [2:0] _PW,
        output _xw
        //output wire [7:0] _tim
    );

    reg [3:0] PC;
    reg xw;
    reg [12:0] PW;
    reg CLKD;
    reg[31:0] CWT;
    reg [7:0] tim;
    wire ST2;
    wire ST5;

    always @(posedge CLK)
        if(CWT <2500000)
            CWT<=CWT+1;
        else
            begin
                CLKD<=~CLKD;
                CWT<=0;
            end

    always @(*)
        case(PC)
            0: PW=12'b000011_000_0000;
            1: PW=12'b010001_001_0001;
            2: PW=12'b000001_010_0111;
            3: PW=12'b000001_011_0010;
            4: PW=12'b010010_001_0100;
            5: PW=12'b000010_100_0001;
            6: PW=12'b000010_101_0101;
            7: PW=12'b101000_001_0111;
            8: PW=12'b001000_011_1000;
            9: PW=12'b000100_111_1001;
            10: PW=12'b000000_000_0000;
        endcase

    always @(*)
        case(PW[6:4])
            0: xw= X1;
            1: xw= 1;
            2: xw= !X2;
            3: xw= !tim;
            4: xw= tim;
            5: xw= X2;
            6: xw= 0;
            7: xw= !X1;
        endcase

        always @(posedge CLKD)
            if(RST) begin PC<=0; tim=0; end
            else
                begin
                    if(xw) PC<=PC+1;
                    else PC<=PW[3:0];
                    if(ST2) tim=20;
                    else if(ST5) tim=50;
                    if(tim) tim=tim-1;
                end


            assign Z1=PW[7];
            assign Z2=PW[8];
            assign Z3=PW[9];
            assign M=PW[10];
            assign ST2=PW[11];
            assign ST5=PW[12];
            assign _tim=tim;
endmodule