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  1.  
  2. [NOTE ] coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 bootblock starting (log level: 7)...
  3. [DEBUG] CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz
  4. [DEBUG] CPU: ID 906c0, Jasperlake A0, ucode: 24000026
  5. [DEBUG] CPU: AES supported, TXT NOT supported, VT supported
  6. [DEBUG] MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1
  7. [DEBUG] PCH: device id 4d87 (rev 01) is Jasperlake Super
  8. [DEBUG] IGD: device id 4e55 (rev 01) is Jasperlake GT4
  9. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0xc04000.
  10. [DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
  11. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  12. [INFO ] CBFS: mcache @0xfef31a00 built for 20 files, used 0x418 of 0x4000 bytes
  13. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x13da0 in mcache @0xfef31a2c
  14. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  15.  
  16.  
  17. [NOTE ] coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 romstage starting (log level: 7)...
  18. [DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
  19. [DEBUG] gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000
  20. [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  21. [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  22. [DEBUG] gpe0_sts[3]: 00000040 gpe0_en[3]: 00000000
  23. [DEBUG] TCO_STS: 0000 0001
  24. [DEBUG] GEN_PMCON: d8a01a38 00002200
  25. [DEBUG] GBLRST_CAUSE: 00000042 00000000
  26. [DEBUG] prev_sleep_state 0 (S0)
  27. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  28. [INFO ] CBFS: Found 'fspm.bin' @0x73dc0 size 0x79000 in mcache @0xfef31cf0
  29. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  30. [DEBUG] SPD INDEX = 0
  31. [INFO ] CBFS: Found 'spd.bin' @0x3b400 size 0x200 in mcache @0xfef31bd8
  32. [INFO ] SPD: module type is LPDDR4X
  33. [INFO ] SPD: module part number is
  34. [INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb
  35. [INFO ] SPD: device width 16 bits, bus width 32 bits
  36. [INFO ] SPD: module size is 4096 MB (per channel)
  37. [DEBUG] CBMEM:
  38. [DEBUG] IMD: root @ 0x76fff000 254 entries.
  39. [DEBUG] IMD: root @ 0x76ffec00 62 entries.
  40. [DEBUG] FMAP: area RO_VPD found @ c00000 (16384 bytes)
  41. [WARN ] init_vpd_rdev: No RW_VPD FMAP section.
  42. [DEBUG] External stage cache:
  43. [DEBUG] IMD: root @ 0x7b3ff000 254 entries.
  44. [DEBUG] IMD: root @ 0x7b3fec00 62 entries.
  45. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  46. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  47. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  48. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  49. [DEBUG] cse_lite: Number of partitions = 3
  50. [DEBUG] cse_lite: Current partition = RW
  51. [DEBUG] cse_lite: Next partition = RW
  52. [DEBUG] cse_lite: Flags = 0x7
  53. [DEBUG] cse_lite: RO version = 13.50.11.1304 (Status=0x0, Start=0x1000, End=0xebfff)
  54. [DEBUG] cse_lite: RW version = 13.50.11.1304 (Status=0x0, Start=0x140000, End=0x2c2fff)
  55. [DEBUG] 2 DIMMs found
  56. [DEBUG] SMM Memory Map
  57. [DEBUG] SMRAM : 0x7b000000 0x800000
  58. [DEBUG] Subregion 0: 0x7b000000 0x200000
  59. [DEBUG] Subregion 1: 0x7b200000 0x200000
  60. [DEBUG] Subregion 2: 0x7b400000 0x400000
  61. [DEBUG] top_of_ram = 0x77000000
  62. [DEBUG] Normal boot
  63. [INFO ] CBFS: Found 'fallback/postcar' @0x123740 size 0x5690 in mcache @0xfef31d64
  64. [DEBUG] Loading module at 0x76c1f000 with entry 0x76c1f031. filesize: 0x5308 memsize: 0xb658
  65. [DEBUG] Processing 210 relocs. Offset value of 0x74c1f000
  66. [DEBUG] BS: romstage times (exec / console): total (unknown) / 2 ms
  67.  
  68.  
  69. [NOTE ] coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 postcar starting (log level: 7)...
  70. [DEBUG] Normal boot
  71. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  72. [INFO ] CBFS: Found 'fallback/ramstage' @0x18f80 size 0x20ee6 in mcache @0x76c2d10c
  73. [DEBUG] Loading module at 0x76ac8000 with entry 0x76ac8000. filesize: 0x48990 memsize: 0x155d90
  74. [DEBUG] Processing 4939 relocs. Offset value of 0x72ac8000
  75. [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
  76.  
  77.  
  78. [NOTE ] coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 ramstage starting (log level: 7)...
  79. [DEBUG] Normal boot
  80. [INFO ] FW_CONFIG value from CBI is 0x300000434
  81. [INFO ] fw_config match found: AUDIO_CODEC_SOURCE=AUDIO_CODEC_UNPROVISIONED
  82. [INFO ] I2C: 00:1a disabled by fw_config
  83. [INFO ] fw_config match found: AUDIO_AMP=UNPROVISIONED
  84. [INFO ] GENERIC: 0.0 disabled by fw_config
  85. [INFO ] USB2 port 3 disabled by fw_config
  86. [INFO ] USB3 port 3 disabled by fw_config
  87. [INFO ] fw_config match found: DB_PORTS=DB_PORTS_1C_1A
  88. [INFO ] fw_config match found: DB_PORTS=DB_PORTS_1C_1A
  89. [DEBUG] microcode: sig=0x906c0 pf=0x1 revision=0x24000026
  90. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  91. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x13ec0 size 0x5000 in mcache @0x76c2d0ac
  92. [INFO ] microcode: Update skipped, already up-to-date
  93. [INFO ] CBFS: Found 'fsps.bin' @0xece00 size 0x36906 in mcache @0x76c2d330
  94. [DEBUG] Detected 2 core, 2 thread CPU.
  95. [DEBUG] Setting up SMI for CPU
  96. [DEBUG] IED base = 0x7b400000
  97. [DEBUG] IED size = 0x00400000
  98. [INFO ] Will perform SMM setup.
  99. [INFO ] CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz.
  100. [INFO ] LAPIC 0x0 in XAPIC mode.
  101. [DEBUG] CPU: APIC: 00 enabled
  102. [DEBUG] CPU: APIC: 01 enabled
  103. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  104. [DEBUG] Processing 16 relocs. Offset value of 0x00030000
  105. [DEBUG] Attempting to start 1 APs
  106. [DEBUG] Waiting for 10ms after sending INIT.
  107. [DEBUG] Waiting for SIPI to complete...
  108. [DEBUG] done.
  109. [DEBUG] Waiting for SIPI to complete...
  110. [DEBUG] done.
  111. [INFO ] LAPIC 0x2 in XAPIC mode.
  112. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x24000026
  113. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x198 memsize: 0x198
  114. [DEBUG] Processing 9 relocs. Offset value of 0x00038000
  115. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  116. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  117. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  118. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x76ae8493
  119. [DEBUG] Installing permanent SMM handler to 0x7b000000
  120. [DEBUG] HANDLER [0x7b1fc000-0x7b1ff9c8]
  121.  
  122. [DEBUG] CPU 0
  123. [DEBUG] ss0 [0x7b1fbc00-0x7b1fc000]
  124. [DEBUG] stub0 [0x7b1f4000-0x7b1f4198]
  125.  
  126. [DEBUG] CPU 1
  127. [DEBUG] ss1 [0x7b1fb800-0x7b1fbc00]
  128. [DEBUG] stub1 [0x7b1f3c00-0x7b1f3d98]
  129.  
  130. [DEBUG] stacks [0x7b000000-0x7b001000]
  131. [DEBUG] Loading module at 0x7b1fc000 with entry 0x7b1fca51. filesize: 0x3900 memsize: 0x39c8
  132. [DEBUG] Processing 183 relocs. Offset value of 0x7b1fc000
  133. [DEBUG] FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
  134. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  135. [DEBUG] smm store: 4 # blocks with size 0x10000
  136. [DEBUG] Loading module at 0x7b1f4000 with entry 0x7b1f4000. filesize: 0x198 memsize: 0x198
  137. [DEBUG] Processing 9 relocs. Offset value of 0x7b1f4000
  138. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  139. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  140. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
  141. [DEBUG] SMM Module: placing smm entry code at 7b1f3c00, cpu # 0x1
  142. [DEBUG] SMM Module: stub loaded at 7b1f4000. Will call 0x7b1fca51
  143. [DEBUG] Clearing SMI status registers
  144. [DEBUG] TCO_STS: INTRD_DET
  145. [DEBUG] GPE0 STD STS: TCO_SCI
  146. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec000, cpu = 0
  147. [DEBUG] In relocation handler: CPU 0
  148. [DEBUG] New SMBASE=0x7b1ec000 IEDBASE=0x7b400000
  149. [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800c00
  150. [DEBUG] Relocation complete.
  151. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ebc00, cpu = 1
  152. [DEBUG] In relocation handler: CPU 1
  153. [DEBUG] New SMBASE=0x7b1ebc00 IEDBASE=0x7b400000
  154. [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800c00
  155. [DEBUG] Relocation complete.
  156. [INFO ] Initializing CPU #0
  157. [DEBUG] CPU: vendor Intel device 906c0
  158. [DEBUG] CPU: family 06, model 9c, stepping 00
  159. [DEBUG] Clearing out pending MCEs
  160. [INFO ] Turbo is available but hidden
  161. [INFO ] Turbo is available and visible
  162. [INFO ] microcode: Update skipped, already up-to-date
  163. [INFO ] CPU #0 initialized
  164. [INFO ] Initializing CPU #1
  165. [DEBUG] CPU: vendor Intel device 906c0
  166. [DEBUG] CPU: family 06, model 9c, stepping 00
  167. [DEBUG] Clearing out pending MCEs
  168. [INFO ] microcode: Update skipped, already up-to-date
  169. [INFO ] CPU #1 initialized
  170. [INFO ] bsp_do_flight_plan done after 1 msecs.
  171. [DEBUG] CPU: frequency set to 2800 MHz
  172. [DEBUG] Enabling SMIs.
  173. [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 41 / 0 ms
  174. [INFO ] Probing TPM: . done!
  175. [INFO ] TPM ready after 0 ms
  176. [INFO ] Connected to device vid:did:rid of 1ae0:0028:00
  177. [INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.7/cr50_v1.9308_B.924-b7eee8833
  178. [INFO ] Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
  179. [INFO ] Initialized TPM device CR50 revision 0
  180. [INFO ] CBFS: Found 'vbt.bin' @0x72e40 size 0x4bd in mcache @0x76c2d268
  181. [INFO ] Found a VBT of 7680 bytes
  182. [DEBUG] WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called
  183. [DEBUG] Detected 2 core, 2 thread CPU.
  184. [DEBUG] Detected 2 core, 2 thread CPU.
  185. [INFO ] FSPS, status=0x00000000
  186. [DEBUG] Display FSP Version Info HOB
  187. [DEBUG] Reference Code - CPU = 8.7.22.30
  188. [DEBUG] uCode Version = 24.0.0.26
  189. [DEBUG] TXT ACM version = ff.ff.ff.ffff
  190. [DEBUG] Reference Code - ME = 8.7.22.30
  191. [DEBUG] MEBx version = 0.0.0.0
  192. [DEBUG] ME Firmware Version = Lite SKU
  193. [DEBUG] Reference Code - PCH = 8.7.22.30
  194. [DEBUG] PCH-CRID Status = Disabled
  195. [DEBUG] PCH-CRID Original Value = ff.ff.ff.ffff
  196. [DEBUG] PCH-CRID New Value = ff.ff.ff.ffff
  197. [DEBUG] OPROM - RST - RAID = ff.ff.ff.ffff
  198. [DEBUG] PCH Hsio Version = 4.0.0.0
  199. [DEBUG] Reference Code - SA - System Agent = 8.7.22.30
  200. [DEBUG] Reference Code - MRC = 0.0.4.68
  201. [DEBUG] SA - PCIe Version = 8.7.22.30
  202. [DEBUG] SA-CRID Status = Disabled
  203. [DEBUG] SA-CRID Original Value = 0.0.0.0
  204. [DEBUG] SA-CRID New Value = 0.0.0.0
  205. [DEBUG] OPROM - VBIOS = ff.ff.ff.ffff
  206. [DEBUG] IO Manageability Engine FW Version = ff.ff.ff.ffff
  207. [DEBUG] PHY Build Version = ff.ff.ff.ffff
  208. [DEBUG] Thunderbolt(TM) FW Version = ff.ff.ff.ffff
  209. [DEBUG] System Agent Manageability Engine FW Version = ff.ff.ff.ffff
  210. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:00:1c.7) which was enabled in devicetree, removing and disabling.
  211. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 395 / 0 ms
  212. [INFO ] Enumerating buses...
  213. [DEBUG] Root Device scanning...
  214. [DEBUG] CPU_CLUSTER: 0 enabled
  215. [DEBUG] DOMAIN: 00000000 enabled
  216. [DEBUG] DOMAIN: 00000000 scanning...
  217. [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
  218. [DEBUG] PCI: 00:00:00.0 [8086/4e22] enabled
  219. [DEBUG] PCI: 00:00:02.0 [8086/4e55] enabled
  220. [DEBUG] PCI: 00:00:04.0 [8086/4e03] enabled
  221. [DEBUG] PCI: 00:00:05.0 [8086/4e19] enabled
  222. [DEBUG] PCI: 00:00:08.0 [8086/4e11] enabled
  223. [DEBUG] PCI: 00:00:14.0 [8086/4ded] enabled
  224. [DEBUG] PCI: 00:00:14.2 [8086/4def] disabled
  225. [DEBUG] PCI: 00:00:14.3 [8086/4df0] enabled
  226. [DEBUG] PCI: 00:00:14.5 [8086/4df8] enabled
  227. [DEBUG] PCI: 00:00:15.0 [8086/4de8] enabled
  228. [DEBUG] PCI: 00:00:15.1 [8086/4de9] enabled
  229. [DEBUG] PCI: 00:00:15.2 [8086/4dea] enabled
  230. [DEBUG] PCI: 00:00:15.3 [8086/4deb] enabled
  231. [DEBUG] PCI: 00:00:16.0 [8086/4de0] enabled
  232. [DEBUG] PCI: 00:00:19.0 [8086/4dc5] enabled
  233. [DEBUG] PCI: 00:00:19.2 [8086/4dc7] enabled
  234. [DEBUG] PCI: 00:00:1a.0 [8086/4dc4] enabled
  235. [DEBUG] PCI: 00:00:1e.0 [8086/4da8] disabled
  236. [DEBUG] PCI: 00:00:1e.2 [8086/4daa] enabled
  237. [DEBUG] PCI: 00:00:1f.0 [8086/4d87] enabled
  238. [INFO ] PCI: Static device PCI: 00:00:1f.1 not found, disabling it.
  239. [DEBUG] RTC Init
  240. [INFO ] Set power on after power failure.
  241. [DEBUG] Disabling Deep S3
  242. [DEBUG] Disabling Deep S3
  243. [DEBUG] Disabling Deep S4
  244. [DEBUG] Disabling Deep S4
  245. [DEBUG] Disabling Deep S5
  246. [DEBUG] Disabling Deep S5
  247. [DEBUG] PCI: 00:00:1f.2 [0000/0000] hidden
  248. [DEBUG] PCI: 00:00:1f.3 [8086/4dc8] enabled
  249. [DEBUG] PCI: 00:00:1f.5 [8086/4da4] enabled
  250. [WARN ] PCI: Leftover static devices:
  251. [WARN ] PCI: 00:00:12.6
  252. [WARN ] PCI: 00:00:09.0
  253. [WARN ] PCI: 00:00:14.1
  254. [WARN ] PCI: 00:00:16.1
  255. [WARN ] PCI: 00:00:16.4
  256. [WARN ] PCI: 00:00:16.5
  257. [WARN ] PCI: 00:00:17.0
  258. [WARN ] PCI: 00:00:19.1
  259. [WARN ] PCI: 00:00:1e.1
  260. [WARN ] PCI: 00:00:1e.3
  261. [WARN ] PCI: 00:00:1f.1
  262. [WARN ] PCI: 00:00:1f.4
  263. [WARN ] PCI: 00:00:1f.7
  264. [WARN ] PCI: Check your devicetree.cb.
  265. [DEBUG] PCI: 00:00:02.0 scanning...
  266. [DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs
  267. [DEBUG] PCI: 00:00:04.0 scanning...
  268. [DEBUG] GENERIC: 0.0 enabled
  269. [DEBUG] bus: PCI: 00:00:04.0->scan_bus: bus PCI: 00:00:04.0 finished in 0 msecs
  270. [DEBUG] PCI: 00:00:05.0 scanning...
  271. [DEBUG] GENERIC: 0.0 enabled
  272. [DEBUG] bus: PCI: 00:00:05.0->scan_bus: bus PCI: 00:00:05.0 finished in 0 msecs
  273. [DEBUG] PCI: 00:00:14.0 scanning...
  274. [DEBUG] USB0 port 0 enabled
  275. [DEBUG] USB0 port 0 scanning...
  276. [DEBUG] USB2 port 0 enabled
  277. [DEBUG] USB2 port 1 enabled
  278. [DEBUG] USB2 port 2 enabled
  279. [DEBUG] USB2 port 3 disabled
  280. [DEBUG] USB2 port 4 disabled
  281. [DEBUG] USB2 port 5 enabled
  282. [DEBUG] USB2 port 6 disabled
  283. [DEBUG] USB2 port 7 enabled
  284. [DEBUG] USB3 port 0 enabled
  285. [DEBUG] USB3 port 1 enabled
  286. [DEBUG] USB3 port 2 enabled
  287. [DEBUG] USB3 port 3 disabled
  288. [DEBUG] USB2 port 3 enabled
  289. [DEBUG] USB3 port 3 enabled
  290. [DEBUG] USB2 port 0 scanning...
  291. [DEBUG] scan_bus: bus USB2 port 0 finished in 0 msecs
  292. [DEBUG] USB2 port 1 scanning...
  293. [DEBUG] scan_bus: bus USB2 port 1 finished in 0 msecs
  294. [DEBUG] USB2 port 2 scanning...
  295. [DEBUG] scan_bus: bus USB2 port 2 finished in 0 msecs
  296. [DEBUG] USB2 port 5 scanning...
  297. [DEBUG] scan_bus: bus USB2 port 5 finished in 0 msecs
  298. [DEBUG] USB2 port 7 scanning...
  299. [DEBUG] scan_bus: bus USB2 port 7 finished in 0 msecs
  300. [DEBUG] USB3 port 0 scanning...
  301. [DEBUG] scan_bus: bus USB3 port 0 finished in 0 msecs
  302. [DEBUG] USB3 port 1 scanning...
  303. [DEBUG] scan_bus: bus USB3 port 1 finished in 0 msecs
  304. [DEBUG] USB3 port 2 scanning...
  305. [DEBUG] scan_bus: bus USB3 port 2 finished in 0 msecs
  306. [DEBUG] USB2 port 3 scanning...
  307. [DEBUG] scan_bus: bus USB2 port 3 finished in 0 msecs
  308. [DEBUG] USB3 port 3 scanning...
  309. [DEBUG] scan_bus: bus USB3 port 3 finished in 0 msecs
  310. [DEBUG] scan_bus: bus USB0 port 0 finished in 0 msecs
  311. [DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs
  312. [DEBUG] PCI: 00:00:14.3 scanning...
  313. [DEBUG] GENERIC: 0.0 enabled
  314. [DEBUG] scan_bus: bus PCI: 00:00:14.3 finished in 0 msecs
  315. [DEBUG] PCI: 00:00:15.0 scanning...
  316. [DEBUG] I2C: 00:15 enabled
  317. [DEBUG] I2C: 00:2c enabled
  318. [DEBUG] scan_bus: bus PCI: 00:00:15.0 finished in 0 msecs
  319. [DEBUG] PCI: 00:00:15.1 scanning...
  320. [DEBUG] scan_bus: bus PCI: 00:00:15.1 finished in 0 msecs
  321. [DEBUG] PCI: 00:00:15.2 scanning...
  322. [DEBUG] GENERIC: 0.0 enabled
  323. [DEBUG] I2C: 00:10 enabled
  324. [DEBUG] I2C: 00:40 enabled
  325. [DEBUG] I2C: 00:5d enabled
  326. [DEBUG] I2C: 00:15 enabled
  327. [DEBUG] I2C: 00:2c enabled
  328. [DEBUG] scan_bus: bus PCI: 00:00:15.2 finished in 0 msecs
  329. [DEBUG] PCI: 00:00:15.3 scanning...
  330. [DEBUG] I2C: 00:36 enabled
  331. [DEBUG] I2C: 00:0c enabled
  332. [DEBUG] I2C: 00:50 enabled
  333. [DEBUG] scan_bus: bus PCI: 00:00:15.3 finished in 0 msecs
  334. [DEBUG] PCI: 00:00:19.0 scanning...
  335. [DEBUG] I2C: 00:1a enabled
  336. [DEBUG] I2C: 00:1a disabled
  337. [DEBUG] scan_bus: bus PCI: 00:00:19.0 finished in 0 msecs
  338. [DEBUG] PCI: 00:00:1e.2 scanning...
  339. [DEBUG] SPI: 00 enabled
  340. [DEBUG] bus: PCI: 00:00:1e.2->scan_bus: bus PCI: 00:00:1e.2 finished in 0 msecs
  341. [DEBUG] PCI: 00:00:1f.0 scanning...
  342. [DEBUG] PNP: 0c09.0 enabled
  343. [DEBUG] PNP: 0c09.0 scanning...
  344. [DEBUG] scan_bus: bus PNP: 0c09.0 finished in 0 msecs
  345. [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs
  346. [DEBUG] PCI: 00:00:1f.3 scanning...
  347. [DEBUG] GENERIC: 0.0 enabled
  348. [DEBUG] GENERIC: 0.0 disabled
  349. [DEBUG] GENERIC: 0.0 enabled
  350. [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
  351. [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1 msecs
  352. [DEBUG] scan_bus: bus Root Device finished in 1 msecs
  353. [INFO ] done
  354. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
  355. [INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'
  356. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  357. [INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  358. [DEBUG] found VGA at PCI: 00:00:02.0
  359. [DEBUG] Setting up VGA for PCI: 00:00:02.0
  360. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
  361. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  362. [INFO ] Allocating resources...
  363. [INFO ] Reading resources...
  364. [DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xc0000000, size = 0x10000000
  365. [DEBUG] SA MMIO resource: MCHBAR -> base = 0xfea80000, size = 0x00008000
  366. [DEBUG] SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000
  367. [DEBUG] SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000
  368. [DEBUG] SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x00001000
  369. [DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
  370. [DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000
  371. [DEBUG] SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x00001000
  372. [DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000
  373. [INFO ] Available memory above 4GB: 6148M
  374. [INFO ] Done reading resources.
  375. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
  376. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
  377. [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  378. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  379. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000800 limit 000008ff io (fixed)
  380. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 00000200 limit 0000020f io (fixed)
  381. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 8c base 00000900 limit 000009ff io (fixed)
  382. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 90 base 00000080 limit 0000008f io (fixed)
  383. [DEBUG] avoid_fixed_resources: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
  384. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 01 base 00001800 limit 000018ff io (fixed)
  385. [INFO ] DOMAIN: 00000000: Resource ranges:
  386. [INFO ] * Base: 1000, Size: 800, Tag: 100
  387. [INFO ] * Base: 1900, Size: e700, Tag: 100
  388. [DEBUG] PCI: 00:00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
  389. [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  390. [DEBUG] DOMAIN: 00000000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff
  391. [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
  392. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base c0000000 limit cfffffff mem (fixed)
  393. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fea80000 limit fea87fff mem (fixed)
  394. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base feda0000 limit feda0fff mem (fixed)
  395. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base feda1000 limit feda1fff mem (fixed)
  396. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fb000000 limit fb000fff mem (fixed)
  397. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed)
  398. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed)
  399. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed92000 limit fed92fff mem (fixed)
  400. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base fed91000 limit fed91fff mem (fixed)
  401. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
  402. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 000c0000 limit 76ffffff mem (fixed)
  403. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 77000000 limit 7fbfffff mem (fixed)
  404. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 100000000 limit 2803fffff mem (fixed)
  405. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
  406. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
  407. [DEBUG] avoid_fixed_resources: PCI: 00:00:19.2 10 base fe032000 limit fe032fff mem (fixed)
  408. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed)
  409. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 10 base fe000000 limit fe00ffff mem (fixed)
  410. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.5 00 base ff000000 limit ffffffff mem (fixed)
  411. [INFO ] DOMAIN: 00000000: Resource ranges:
  412. [INFO ] * Base: 7fc00000, Size: 40400000, Tag: 200
  413. [INFO ] * Base: d0000000, Size: 10000000, Tag: 200
  414. [INFO ] * Base: 280400000, Size: 7d7fc00000, Tag: 200
  415. [DEBUG] PCI: 00:00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  416. [DEBUG] PCI: 00:00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
  417. [DEBUG] PCI: 00:00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
  418. [DEBUG] PCI: 00:00:1f.3 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
  419. [DEBUG] PCI: 00:00:04.0 10 * [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem
  420. [DEBUG] PCI: 00:00:14.0 10 * [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem
  421. [DEBUG] PCI: 00:00:14.3 10 * [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem
  422. [DEBUG] PCI: 00:00:1f.3 10 * [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem
  423. [DEBUG] PCI: 00:00:08.0 10 * [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem
  424. [DEBUG] PCI: 00:00:14.5 10 * [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem
  425. [DEBUG] PCI: 00:00:15.0 10 * [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem
  426. [DEBUG] PCI: 00:00:15.1 10 * [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem
  427. [DEBUG] PCI: 00:00:15.2 10 * [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem
  428. [DEBUG] PCI: 00:00:15.3 10 * [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem
  429. [DEBUG] PCI: 00:00:16.0 10 * [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem
  430. [DEBUG] PCI: 00:00:19.0 10 * [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem
  431. [DEBUG] PCI: 00:00:19.2 18 * [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem
  432. [DEBUG] PCI: 00:00:1a.0 10 * [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem
  433. [DEBUG] PCI: 00:00:1e.2 10 * [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem
  434. [DEBUG] PCI: 00:00:1f.5 10 * [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem
  435. [DEBUG] DOMAIN: 00000000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff done
  436. [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  437. [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
  438. [DEBUG] PCI: 00:00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
  439. [DEBUG] PCI: 00:00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
  440. [DEBUG] PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
  441. [DEBUG] PCI: 00:00:04.0 10 <- [0x000000007fd00000 - 0x000000007fd0ffff] size 0x00010000 gran 0x10 mem64
  442. [DEBUG] PCI: 00:00:05.0 10 <- [0x0000000091000000 - 0x0000000091ffffff] size 0x01000000 gran 0x18 mem64
  443. [DEBUG] PCI: 00:00:08.0 10 <- [0x000000007fd28000 - 0x000000007fd28fff] size 0x00001000 gran 0x0c mem64
  444. [DEBUG] PCI: 00:00:14.0 10 <- [0x000000007fd10000 - 0x000000007fd1ffff] size 0x00010000 gran 0x10 mem64
  445. [DEBUG] PCI: 00:00:14.3 10 <- [0x000000007fd20000 - 0x000000007fd23fff] size 0x00004000 gran 0x0e mem64
  446. [DEBUG] PCI: 00:00:14.5 10 <- [0x000000007fd29000 - 0x000000007fd29fff] size 0x00001000 gran 0x0c mem64
  447. [DEBUG] PCI: 00:00:15.0 10 <- [0x000000007fd2a000 - 0x000000007fd2afff] size 0x00001000 gran 0x0c mem64
  448. [DEBUG] PCI: 00:00:15.1 10 <- [0x000000007fd2b000 - 0x000000007fd2bfff] size 0x00001000 gran 0x0c mem64
  449. [DEBUG] PCI: 00:00:15.2 10 <- [0x000000007fd2c000 - 0x000000007fd2cfff] size 0x00001000 gran 0x0c mem64
  450. [DEBUG] PCI: 00:00:15.3 10 <- [0x000000007fd2d000 - 0x000000007fd2dfff] size 0x00001000 gran 0x0c mem64
  451. [DEBUG] PCI: 00:00:16.0 10 <- [0x000000007fd2e000 - 0x000000007fd2efff] size 0x00001000 gran 0x0c mem64
  452. [DEBUG] PCI: 00:00:19.0 10 <- [0x000000007fd2f000 - 0x000000007fd2ffff] size 0x00001000 gran 0x0c mem64
  453. [DEBUG] PCI: 00:00:19.2 18 <- [0x000000007fd30000 - 0x000000007fd30fff] size 0x00001000 gran 0x0c mem64
  454. [DEBUG] PCI: 00:00:1a.0 10 <- [0x000000007fd31000 - 0x000000007fd31fff] size 0x00001000 gran 0x0c mem64
  455. [DEBUG] PCI: 00:00:1e.2 10 <- [0x000000007fd32000 - 0x000000007fd32fff] size 0x00001000 gran 0x0c mem64
  456. [DEBUG] PCI: 00:00:1f.3 10 <- [0x000000007fd24000 - 0x000000007fd27fff] size 0x00004000 gran 0x0e mem64
  457. [DEBUG] PCI: 00:00:1f.3 20 <- [0x000000007fc00000 - 0x000000007fcfffff] size 0x00100000 gran 0x14 mem64
  458. [DEBUG] PCI: 00:00:1f.5 10 <- [0x000000007fd33000 - 0x000000007fd33fff] size 0x00001000 gran 0x0c mem
  459. [INFO ] Done setting resources.
  460. [INFO ] Done allocating resources.
  461. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 0 ms
  462. [DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 1 / 0 ms
  463. [INFO ] Enabling resources...
  464. [DEBUG] PCI: 00:00:00.0 subsystem <- 8086/4e22
  465. [DEBUG] PCI: 00:00:00.0 cmd <- 06
  466. [DEBUG] PCI: 00:00:02.0 subsystem <- 8086/4e55
  467. [DEBUG] PCI: 00:00:02.0 cmd <- 03
  468. [DEBUG] PCI: 00:00:04.0 subsystem <- 8086/4e03
  469. [DEBUG] PCI: 00:00:04.0 cmd <- 02
  470. [DEBUG] PCI: 00:00:05.0 bridge ctrl <- 0003
  471. [DEBUG] PCI: 00:00:05.0 subsystem <- 8086/4e19
  472. [DEBUG] PCI: 00:00:05.0 cmd <- 02
  473. [DEBUG] PCI: 00:00:08.0 subsystem <- 8086/4e11
  474. [DEBUG] PCI: 00:00:08.0 cmd <- 06
  475. [DEBUG] PCI: 00:00:14.0 subsystem <- 8086/4ded
  476. [DEBUG] PCI: 00:00:14.0 cmd <- 02
  477. [DEBUG] PCI: 00:00:14.3 subsystem <- 8086/4df0
  478. [DEBUG] PCI: 00:00:14.3 cmd <- 02
  479. [DEBUG] PCI: 00:00:14.5 subsystem <- 8086/4df8
  480. [DEBUG] PCI: 00:00:14.5 cmd <- 06
  481. [DEBUG] PCI: 00:00:15.0 subsystem <- 8086/4de8
  482. [DEBUG] PCI: 00:00:15.0 cmd <- 02
  483. [DEBUG] PCI: 00:00:15.1 subsystem <- 8086/4de9
  484. [DEBUG] PCI: 00:00:15.1 cmd <- 02
  485. [DEBUG] PCI: 00:00:15.2 subsystem <- 8086/4dea
  486. [DEBUG] PCI: 00:00:15.2 cmd <- 02
  487. [DEBUG] PCI: 00:00:15.3 subsystem <- 8086/4deb
  488. [DEBUG] PCI: 00:00:15.3 cmd <- 02
  489. [DEBUG] PCI: 00:00:16.0 subsystem <- 8086/4de0
  490. [DEBUG] PCI: 00:00:16.0 cmd <- 02
  491. [DEBUG] PCI: 00:00:19.0 subsystem <- 8086/4dc5
  492. [DEBUG] PCI: 00:00:19.0 cmd <- 02
  493. [DEBUG] PCI: 00:00:19.2 subsystem <- 8086/4dc7
  494. [DEBUG] PCI: 00:00:19.2 cmd <- 06
  495. [DEBUG] PCI: 00:00:1a.0 subsystem <- 8086/4dc4
  496. [DEBUG] PCI: 00:00:1a.0 cmd <- 06
  497. [DEBUG] PCI: 00:00:1e.2 subsystem <- 8086/4daa
  498. [DEBUG] PCI: 00:00:1e.2 cmd <- 06
  499. [DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/4d87
  500. [DEBUG] PCI: 00:00:1f.0 cmd <- 407
  501. [DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/4dc8
  502. [DEBUG] PCI: 00:00:1f.3 cmd <- 02
  503. [DEBUG] PCI: 00:00:1f.5 subsystem <- 8086/4da4
  504. [DEBUG] PCI: 00:00:1f.5 cmd <- 406
  505. [INFO ] done.
  506. [INFO ] Initializing devices...
  507. [DEBUG] Root Device init
  508. [INFO ] mainboard: EC init
  509. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
  510. [DEBUG] Chrome EC: UHEPI supported
  511. [DEBUG] Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
  512. [DEBUG] Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
  513. [DEBUG] Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001009105e
  514. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  515. [DEBUG] Root Device init finished in 4 msecs
  516. [DEBUG] PCI: 00:00:00.0 init
  517. [INFO ] CPU TDP = 6 Watts
  518. [INFO ] CPU PL1 = 6 Watts
  519. [INFO ] CPU PL2 = 20 Watts
  520. [DEBUG] PCI: 00:00:00.0 init finished in 1 msecs
  521. [DEBUG] PCI: 00:00:02.0 init
  522. [INFO ] GMA: Found VBT in CBFS
  523. [INFO ] GMA: Found valid VBT in CBFS
  524. [INFO ] framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
  525. [INFO ] x_res x y_res: 1366 x 768, size: 4227072 at 0x80000000
  526. [DEBUG] PCI: 00:00:02.0 init finished in 0 msecs
  527. [DEBUG] PCI: 00:00:08.0 init
  528. [DEBUG] PCI: 00:00:08.0 init finished in 0 msecs
  529. [DEBUG] PCI: 00:00:14.0 init
  530. [DEBUG] XHCI: Updated LFPS sampling OFF time to 9 ms
  531. [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
  532. [DEBUG] PCI: 00:00:15.0 init
  533. [DEBUG] I2C bus 0 version 0x3230302a
  534. [INFO ] DW I2C bus 0 at 0x7fd2a000 (400 KHz)
  535. [DEBUG] PCI: 00:00:15.0 init finished in 0 msecs
  536. [DEBUG] PCI: 00:00:15.1 init
  537. [DEBUG] I2C bus 1 version 0x3230302a
  538. [INFO ] DW I2C bus 1 at 0x7fd2b000 (400 KHz)
  539. [DEBUG] PCI: 00:00:15.1 init finished in 0 msecs
  540. [DEBUG] PCI: 00:00:15.2 init
  541. [DEBUG] I2C bus 2 version 0x3230302a
  542. [INFO ] DW I2C bus 2 at 0x7fd2c000 (400 KHz)
  543. [DEBUG] PCI: 00:00:15.2 init finished in 0 msecs
  544. [DEBUG] PCI: 00:00:15.3 init
  545. [DEBUG] I2C bus 3 version 0x3230302a
  546. [INFO ] DW I2C bus 3 at 0x7fd2d000 (400 KHz)
  547. [DEBUG] PCI: 00:00:15.3 init finished in 0 msecs
  548. [DEBUG] PCI: 00:00:16.0 init
  549. [DEBUG] PCI: 00:00:16.0 init finished in 0 msecs
  550. [DEBUG] PCI: 00:00:19.0 init
  551. [DEBUG] I2C bus 4 version 0x3230302a
  552. [INFO ] DW I2C bus 4 at 0x7fd2f000 (400 KHz)
  553. [DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
  554. [DEBUG] PCI: 00:00:1a.0 init
  555. [DEBUG] PCI: 00:00:1a.0 init finished in 0 msecs
  556. [DEBUG] PCI: 00:00:1f.0 init
  557. [DEBUG] IOAPIC: Initializing IOAPIC at fec00000
  558. [DEBUG] IOAPIC: ID = 0x00
  559. [DEBUG] IOAPIC: 120 interrupts
  560. [DEBUG] IOAPIC: Clearing IOAPIC at fec00000
  561. [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
  562. [DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs
  563. [DEBUG] PCI: 00:00:1f.2 init
  564. [DEBUG] apm_control: Disabling ACPI.
  565. [DEBUG] APMC done.
  566. [DEBUG] PCI: 00:00:1f.2 init finished in 4 msecs
  567. [DEBUG] PCI: 00:00:1f.3 init
  568. [DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
  569. [DEBUG] PNP: 0c09.0 init
  570. [DEBUG] Google Chrome EC uptime: 458349.255 seconds
  571. [DEBUG] Google Chrome AP resets since EC boot: 2
  572. [DEBUG] Google Chrome most recent AP reset causes:
  573. [DEBUG] 0.492: 32775 shutdown: entering G3
  574. [DEBUG] 451317.302: 32775 shutdown: entering G3
  575. [DEBUG] Google Chrome EC reset flags at last EC boot: reset-pin | power-on | sysjump
  576. [DEBUG] Google Chrome EC: version:
  577. [DEBUG] ro: drawcia_v2.0.6194-efc4ddb72
  578. [DEBUG] rw: drawcia_v2.0.6194-efc4ddb72
  579. [DEBUG] running image: 2
  580. [DEBUG] ChromeEC SW Sync: Checking for EC_RW update
  581. [INFO ] CBFS: Found 'ecrw.hash' @0x72dc0 size 0x20 in mcache @0x76c2d244
  582. [DEBUG] ChromeEC SW Sync: Expected hash: d7aaf3847f2ca17f21ca2b3f6d62e00367c38004e4797c0266215f2734b165b3
  583. [DEBUG] ChromeEC SW Sync: current EC_RW hash: 31c7ca38ab159ecda709938b064164ff676c8845e05e779346a167e7e291dfa1
  584. [DEBUG] ChromeEC SW Sync: updating EC_RW...
  585. [INFO ] CBFS: Found 'ecrw' @0x3ebc0 size 0x341b8 in mcache @0x76c2d224
  586. [DEBUG] ChromeEC SW Sync: failed to erase flash
  587. [ERROR] ChromeEC SW Sync: Failed to update EC_RW.
  588. [ERROR] ChromeEC SW Sync: EC SW SYNC FAILED
  589. [DEBUG] PNP: 0c09.0 init finished in 11 msecs
  590. [INFO ] Devices initialized
  591. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 23 / 0 ms
  592. [INFO ] tlcl2_send_startup: Startup return code is 0x0
  593. [INFO ] TPM: setup succeeded
  594. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 60 / 0 ms
  595. [INFO ] Finalize devices...
  596. [DEBUG] PCI: 00:00:02.0 final
  597. [DEBUG] PCI: 00:00:16.0 final
  598. [DEBUG] CSE RW Firmware Version: 0.0.0.0
  599. [DEBUG] PCI: 00:00:1f.2 final
  600. [INFO ] Devices finalized
  601. [DEBUG] ME: HFSTS1 : 0x90000245
  602. [DEBUG] ME: HFSTS2 : 0x86100126
  603. [DEBUG] ME: HFSTS3 : 0x00000050
  604. [DEBUG] ME: HFSTS4 : 0x00004004
  605. [DEBUG] ME: HFSTS5 : 0x00000000
  606. [DEBUG] ME: HFSTS6 : 0x00400006
  607. [DEBUG] ME: Manufacturing Mode : NO
  608. [DEBUG] ME: SPI Protection Mode Enabled : YES
  609. [DEBUG] ME: FW Partition Table : OK
  610. [DEBUG] ME: Bringup Loader Failure : NO
  611. [DEBUG] ME: Firmware Init Complete : YES
  612. [DEBUG] ME: Boot Options Present : NO
  613. [DEBUG] ME: Update In Progress : NO
  614. [DEBUG] ME: D0i3 Support : YES
  615. [DEBUG] ME: Low Power State Enabled : NO
  616. [DEBUG] ME: CPU Replaced : NO
  617. [DEBUG] ME: CPU Replacement Valid : YES
  618. [DEBUG] ME: Current Working State : 5
  619. [DEBUG] ME: Current Operation State : 1
  620. [DEBUG] ME: Current Operation Mode : 0
  621. [DEBUG] ME: Error Code : 0
  622. [DEBUG] ME: CPU Debug Disabled : YES
  623. [DEBUG] ME: TXT Support : NO
  624. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3b640 size 0x353b in mcache @0x76c2d1f8
  625. [WARN ] CBFS: 'fallback/slic' not found.
  626. [INFO ] ACPI: Writing ACPI tables at 76a37000.
  627. [DEBUG] ACPI: * FACS
  628. [DEBUG] SCI is IRQ 9, GSI 9
  629. [DEBUG] ACPI: * FACP
  630. [DEBUG] ACPI: added table 1/32, length now 44
  631. [DEBUG] Found 1 CPU(s) with 2/2 physical/logical core(s) each.
  632. [DEBUG] PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
  633. [DEBUG] Empty min sleep state array returned
  634. [INFO ] Returning default LPI constraint package
  635. [INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in
  636. [INFO ] \_SB.DPTF: Intel DPTF at GENERIC: 0.0
  637. [INFO ] \_SB.PCI0.IPU0.IPU0: Intel MIPI Camera Device I2C address 00h
  638. [INFO ] \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
  639. [INFO ] \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 00:15
  640. [INFO ] \_SB.PCI0.I2C3.CAM1: Intel MIPI Camera Device I2C address 036h
  641. [INFO ] \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device I2C address 0ch
  642. [INFO ] \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device I2C address 050h
  643. [INFO ] \_SB.PCI0.I2C4.RT58: Headset Codec at I2C: 00:1a
  644. [INFO ] \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
  645. [INFO ] PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
  646. [INFO ] PS2K: Passing 80 keymaps to kernel
  647. [INFO ] PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
  648. [INFO ] \_SB.PCI0.HDAS.MAXM: Maxim Integrated 98357A Amplifier
  649. [INFO ] \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
  650. [INFO ] \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1
  651. [INFO ] \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2
  652. [INFO ] \_SB.PCI0.XHCI.RHUB.HS06: Camera at USB2 port 5
  653. [INFO ] \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7
  654. [INFO ] \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
  655. [INFO ] \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1
  656. [INFO ] \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
  657. [INFO ] \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3
  658. [INFO ] \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port at USB3 port 3
  659. [DEBUG] ACPI: * SSDT
  660. [DEBUG] ACPI: added table 2/32, length now 52
  661. [DEBUG] ACPI: * MCFG
  662. [DEBUG] ACPI: added table 3/32, length now 60
  663. [DEBUG] TPM2 log created at 0x76a27000
  664. [DEBUG] ACPI: * TPM2
  665. [DEBUG] ACPI: added table 4/32, length now 68
  666. [DEBUG] ACPI: * LPIT
  667. [DEBUG] ACPI: added table 5/32, length now 76
  668. [DEBUG] IOAPIC: 120 interrupts
  669. [DEBUG] SCI is IRQ 9, GSI 9
  670. [DEBUG] ACPI: * APIC
  671. [DEBUG] ACPI: added table 6/32, length now 84
  672. [DEBUG] current = 76a3d620
  673. [DEBUG] ACPI: * DMAR
  674. [DEBUG] ACPI: added table 7/32, length now 92
  675. [DEBUG] ACPI: added table 8/32, length now 100
  676. [DEBUG] ACPI: * HPET
  677. [DEBUG] ACPI: added table 9/32, length now 108
  678. [INFO ] ACPI: done.
  679. [DEBUG] ACPI tables: 26480 bytes.
  680. [DEBUG] smbios_write_tables: 76a1f000
  681. [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-2405.0'
  682. [INFO ] Create SMBIOS type 16
  683. [INFO ] Create SMBIOS type 17
  684. [INFO ] Create SMBIOS type 20
  685. [INFO ] GENERIC: 0.0 (WIFI Device)
  686. [DEBUG] SMBIOS tables: 1028 bytes.
  687. [DEBUG] Writing table forward entry at 0x00000500
  688. [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d938
  689. [DEBUG] Writing coreboot table at 0x76a5b000
  690. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  691. [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
  692. [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
  693. [DEBUG] 3. 0000000000100000-0000000076a1efff: RAM
  694. [DEBUG] 4. 0000000076a1f000-0000000076ac7fff: CONFIGURATION TABLES
  695. [DEBUG] 5. 0000000076ac8000-0000000076c1dfff: RAMSTAGE
  696. [DEBUG] 6. 0000000076c1e000-0000000076ffffff: CONFIGURATION TABLES
  697. [DEBUG] 7. 0000000077000000-000000007fbfffff: RESERVED
  698. [DEBUG] 8. 00000000c0000000-00000000cfffffff: RESERVED
  699. [DEBUG] 9. 00000000fb000000-00000000fb000fff: RESERVED
  700. [DEBUG] 10. 00000000fe000000-00000000fe00ffff: RESERVED
  701. [DEBUG] 11. 00000000fe0b0000-00000000fe0bffff: RESERVED
  702. [DEBUG] 12. 00000000fea80000-00000000fea87fff: RESERVED
  703. [DEBUG] 13. 00000000fed80000-00000000fed83fff: RESERVED
  704. [DEBUG] 14. 00000000fed90000-00000000fed92fff: RESERVED
  705. [DEBUG] 15. 00000000feda0000-00000000feda1fff: RESERVED
  706. [DEBUG] 16. 00000000ff000000-00000000ffffffff: RESERVED
  707. [DEBUG] 17. 0000000100000000-00000002803fffff: RAM
  708. [DEBUG] FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
  709. [DEBUG] smm store: 4 # blocks with size 0x10000
  710. [INFO ] Board ID: 4
  711. [INFO ] FW config: 0x300000434
  712. [DEBUG] Wrote coreboot table at: 0x76a5b000, 0x574 bytes, checksum 3718
  713. [DEBUG] coreboot table: 1420 bytes.
  714. [DEBUG] IMD ROOT 0. 0x76fff000 0x00001000
  715. [DEBUG] IMD SMALL 1. 0x76ffe000 0x00001000
  716. [DEBUG] FSP MEMORY 2. 0x76c4e000 0x003b0000
  717. [DEBUG] CONSOLE 3. 0x76c2e000 0x00020000
  718. [DEBUG] RO MCACHE 4. 0x76c2d000 0x00000418
  719. [DEBUG] TIME STAMP 5. 0x76c2c000 0x00000910
  720. [DEBUG] MEM INFO 6. 0x76c2b000 0x00000f48
  721. [DEBUG] AFTER CAR 7. 0x76c1e000 0x0000d000
  722. [DEBUG] RAMSTAGE 8. 0x76ac7000 0x00157000
  723. [DEBUG] REFCODE 9. 0x76a87000 0x00040000
  724. [DEBUG] SMM BACKUP 10. 0x76a77000 0x00010000
  725. [DEBUG] SMM COMBUFFER11. 0x76a67000 0x00010000
  726. [DEBUG] IGD OPREGION12. 0x76a63000 0x00003c43
  727. [DEBUG] COREBOOT 13. 0x76a5b000 0x00008000
  728. [DEBUG] ACPI 14. 0x76a37000 0x00024000
  729. [DEBUG] TPM2 TCGLOG15. 0x76a27000 0x00010000
  730. [DEBUG] SMBIOS 16. 0x76a1f000 0x00008000
  731. [DEBUG] IMD small region:
  732. [DEBUG] IMD ROOT 0. 0x76ffec00 0x00000400
  733. [DEBUG] FSP RUNTIME 1. 0x76ffebe0 0x00000004
  734. [DEBUG] VPD 2. 0x76ffe9a0 0x00000229
  735. [DEBUG] FMAP 3. 0x76ffe800 0x00000188
  736. [DEBUG] CSE BP INFO 4. 0x76ffe780 0x00000068
  737. [DEBUG] CSE SPECIFIC INFO 5. 0x76ffe760 0x00000020
  738. [DEBUG] POWER STATE 6. 0x76ffe720 0x00000040
  739. [DEBUG] FSPM VERSION 7. 0x76ffe700 0x00000004
  740. [DEBUG] ROMSTAGE 8. 0x76ffe6e0 0x00000004
  741. [DEBUG] ROMSTG STCK 9. 0x76ffe620 0x000000a8
  742. [DEBUG] ACPI GNVS 10. 0x76ffe5e0 0x00000038
  743. [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 11 / 0 ms
  744. [INFO ] LAPIC 0x0 in XAPIC mode.
  745. [DEBUG] MTRR: Physical address space:
  746. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  747. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  748. [DEBUG] 0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
  749. [DEBUG] 0x0000000077000000 - 0x000000007fffffff size 0x09000000 type 0
  750. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  751. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  752. [DEBUG] 0x0000000100000000 - 0x00000002803fffff size 0x180400000 type 6
  753. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
  754. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
  755. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
  756. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
  757. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
  758. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
  759. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
  760. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
  761. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
  762. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
  763. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
  764. [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
  765. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/6.
  766. [DEBUG] MTRR: UC selected as default type.
  767. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  768. [DEBUG] MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
  769. [DEBUG] MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
  770. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
  771. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  772. [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
  773. [INFO ] LAPIC 0x2 in XAPIC mode.
  774. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
  775. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
  776. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
  777. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
  778. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
  779. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
  780. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
  781. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
  782. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
  783. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
  784. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
  785. [DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
  786. [DEBUG] MTRR: TEMPORARY Physical address space:
  787. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  788. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  789. [DEBUG] 0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
  790. [DEBUG] 0x0000000077000000 - 0x00000000feffffff size 0x88000000 type 0
  791. [DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
  792. [DEBUG] 0x0000000100000000 - 0x00000002803fffff size 0x180400000 type 6
  793. [DEBUG] MTRR: default type WB/UC MTRR counts: 10/6.
  794. [DEBUG] MTRR: UC selected as default type.
  795. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  796. [DEBUG] MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
  797. [DEBUG] MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
  798. [DEBUG] MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
  799. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  800. [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
  801.  
  802. [DEBUG] MTRR check
  803. [DEBUG] Fixed MTRRs : Enabled
  804. [DEBUG] Variable MTRRs: Enabled
  805.  
  806. [INFO ] CBFS: Found 'fallback/payload' @0x128e40 size 0x13eb48 in mcache @0x76c2d3a8
  807. [DEBUG] Checking segment from ROM address 0xffd2d06c
  808. [DEBUG] Checking segment from ROM address 0xffd2d088
  809. [DEBUG] Loading segment from ROM address 0xffd2d06c
  810. [DEBUG] code (compression=1)
  811. [DEBUG] New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd2d0a4 filesize 0x13eb10
  812. [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x000000000013eb10
  813. [DEBUG] using LZMA
  814. [DEBUG] Loading segment from ROM address 0xffd2d088
  815. [DEBUG] Entry Point 0x008016b3
  816. [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 728 / 0 ms
  817. [DEBUG] Finalizing chipset.
  818. [DEBUG] apm_control: Finalizing SMM.
  819. [DEBUG] APMC done.
  820. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
  821. [INFO ] HECI: Sending End-of-Post
  822. [INFO ] CSE: EOP requested action: continue boot
  823. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 10 / 0 ms
  824. [DEBUG] mp_park_aps done after 0 msecs.
  825. [DEBUG] Jumping to boot code at 0x008016b3(0x76a5b000)
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