module ratedivider(enable,d, q, Clock, par_load, clear_b, SW);
input enable;
input par_load;
input Clock;
input clear_b;
input [1:0] SW;

output reg [27:0] q;
output reg [27:0] d;

always @(*)
	begin
		case ({SW[1], SW[0]})
			2'b00: d = 28'b0000000000000000000000000000;
			2'b01: d = 28'b0010111110101111000001111111; //50m - 1
			2'b10: d = 28'b0101111101011110000011111111; //100m - 1
			2'b11: d = 28'b1011111010111100000111111111; //200m - 1
		endcase
	end

always @(posedge Clock)
	begin
		if (clear_b == 1'b0)
			q <= 28'b0000000000000000000000000000;
		else if (par_load == 1'b1)
			q <= d;
		else if (enable == 1'b1)
			begin
				if (q == 28'b0000000000000000000000000000)
					q <= d;
				else
					q <= q - 1'b1;
			end
	end
endmodule