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ayankh

Xen device tree

Jun 15th, 2023 (edited)
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x02>;
  5. #size-cells = <0x02>;
  6. interrupt-parent = <0x01>;
  7. model = "Generated";
  8. compatible = "xlnx,versal-net";
  9.  
  10. memory@100000 {
  11. #address-cells = <0x02>;
  12. #size-cells = <0x02>;
  13. device_type = "memory";
  14. reg = <0x00 0x100000 0x00 0x20000000>;
  15. };
  16.  
  17. chosen {
  18. xen,xen-bootargs = "console=dtuart dtuart=serial0";
  19. #mpu,address-cells = <0x01>;
  20. #mpu,size-cells = <0x01>;
  21. mpu,boot-module-section = <0xa00000 0x300000>;
  22. mpu,guest-memory-section = <0xd00000 0x1000000>;
  23. mpu,device-memory-section = <0x80000000 0x7ffff000>;
  24. xen,static-heap = <0x0 0x1d00000 0x0 0x800000>;
  25.  
  26. domU1 {
  27. compatible = "xen,domain";
  28. #address-cells = <0x01>;
  29. #size-cells = <0x01>;
  30. cpus = <0x02>;
  31. memory = <0x00 0x2000>;
  32. direct-map;
  33. vpl011;
  34. mpu;
  35. #xen,static-mem-address-cells = <0x01>;
  36. #xen,static-mem-size-cells = <0x01>;
  37. xen,static-mem = <0x0 0xd00000 0x0 0x800000>;
  38.  
  39. module@b00000 {
  40. compatible = "multiboot,kernel\0multiboot,module";
  41. reg = <0xb00000 0x80000>;
  42. };
  43.  
  44. module@b80000 {
  45. compatible = "multiboot,device-tree\0multiboot,module";
  46. reg = <0xb80000 0x10000>;
  47. };
  48. };
  49.  
  50. domU2 {
  51. compatible = "xen,domain";
  52. #address-cells = <0x01>;
  53. #size-cells = <0x01>;
  54. cpus = <0x02>;
  55. memory = <0x00 0x2000>;
  56. direct-map;
  57. vpl011;
  58. mpu;
  59. #xen,static-mem-address-cells = <0x01>;
  60. #xen,static-mem-size-cells = <0x01>;
  61. xen,static-mem = <0x0 0x1500000 0x0 0x800000>;
  62.  
  63. module@c00000 {
  64. compatible = "multiboot,kernel\0multiboot,module";
  65. reg = <0xc00000 0x80000>;
  66. };
  67.  
  68. module@c80000 {
  69. compatible = "multiboot,device-tree\0multiboot,module";
  70. reg = <0xc80000 0x10000>;
  71. };
  72. };
  73. };
  74.  
  75. cpus {
  76. #address-cells = <0x02>;
  77. #size-cells = <0x00>;
  78.  
  79. cpu-map {
  80.  
  81. cluster0 {
  82.  
  83. core0 {
  84.  
  85. thread0 {
  86. cpu = <0x02>;
  87. };
  88. };
  89. core1 {
  90.  
  91. thread0 {
  92. cpu = <0x03>;
  93. };
  94. };
  95. };
  96. };
  97.  
  98. cpu@0 {
  99. device_type = "cpu";
  100. compatible = "arm,armv8";
  101. reg = <0x00 0x00>;
  102. phandle = <0x02>;
  103. };
  104.  
  105. cpu@1 {
  106. device_type = "cpu";
  107. compatible = "arm,armv8";
  108. reg = <0x00 0x01>;
  109. phandle = <0x03>;
  110. };
  111. };
  112.  
  113. interrupt-controller@e2000000 {
  114. compatible = "arm,gic-v3";
  115. #interrupt-cells = <0x03>;
  116. reg = <0x00 0xe2000000 0x00 0x10000 0x00 0xe2100000 0x00 0x200000 0x00 0xe2060000 0x00 0x200000>;
  117. interrupt-controller;
  118. interrupts = <0x01 0x09 0x04>;
  119. phandle = <0x01>;
  120. };
  121.  
  122. serial@f1920000 {
  123. u-boot,dm-pre-reloc;
  124. compatible = "arm,pl011\0arm,sbsa-uart";
  125. reg = <0x00 0xf1920000 0x00 0x1000>;
  126. interrupts = <0x00 0x19 0x04>;
  127. clock-names = "uartclk\0apb_pclk";
  128. clocks = <0x11 0x11>;
  129. clock = <0xf4240>;
  130. current-speed = <0x1c200>;
  131. skip-init;
  132. phandle = <0x2e>;
  133. };
  134.  
  135. timer@f1dc0000 {
  136. compatible = "cdns,ttc";
  137. interrupt-parent = <0x01>;
  138. interrupts = <0x00 0x2b 0x04 0x00 0x2c 0x04 0x00 0x2d 0x04>;
  139. timer-width = <0x20>;
  140. reg = <0x00 0xf1dc0000 0x00 0x1000>;
  141. clocks = <0x0c 0x27 0x0c 0x52>;
  142. power-domains = <0x0d 0x18224024>;
  143. phandle = <0x33>;
  144. status = "okay";
  145. xen,passthrough;
  146. };
  147.  
  148. timer@f1dd0000 {
  149. compatible = "cdns,ttc";
  150. interrupt-parent = <0x01>;
  151. interrupts = <0x00 0x2e 0x04 0x00 0x2f 0x04 0x00 0x30 0x04>;
  152. timer-width = <0x20>;
  153. reg = <0x00 0xf1dd0000 0x00 0x1000>;
  154. clocks = <0x0c 0x27 0x0c 0x52>;
  155. power-domains = <0x0d 0x18224024>;
  156. phandle = <0x34>;
  157. status = "okay";
  158. xen,passthrough;
  159. };
  160.  
  161. clk1 {
  162. u-boot,dm-pre-reloc;
  163. compatible = "fixed-clock";
  164. #clock-cells = <0x00>;
  165. clock-frequency = <0xf4240>;
  166. phandle = <0x11>;
  167. };
  168.  
  169. timer {
  170. compatible = "arm,armv8-timer";
  171. interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
  172. phandle = <0x15>;
  173. };
  174.  
  175. aliases {
  176. serial0 = "/serial@f1920000";
  177. };
  178. };
  179.  
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