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- `timescale 1ns / 1ps
- ////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 15:02:01 06/20/2018
- // Design Name: zamek
- // Module Name: C:/Documents and Settings/student/Pulpit/Nowy folder/Projekt_here/test.v
- // Project Name: Projekt_here
- // Target Device:
- // Tool versions:
- // Description:
- //
- // Verilog Test Fixture created by ISE for module: zamek
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- ////////////////////////////////////////////////////////////////////////////////
- module test;
- // Inputs
- reg K1;
- reg K2;
- reg K3;
- reg K4;
- reg RST;
- reg CLK;
- reg RESET;
- // Outputs
- wire SET;
- wire OTW;
- wire ALARM;
- wire S1_LED;
- wire WORK;
- wire [5:0] _stan;
- wire [2:0] _licznik;
- // Instantiate the Unit Under Test (UUT)
- zamek uut (
- .K1(K1),
- .K2(K2),
- .K3(K3),
- .K4(K4),
- .RST(RST),
- .CLK(CLK),
- .RESET(RESET),
- .SET(SET),
- .OTW(OTW),
- .ALARM(ALARM),
- .S1_LED(S1_LED),
- .WORK(WORK),
- ._stan(_stan),
- ._licznik(_licznik)
- );
- always #50 CLK=~CLK;
- initial begin
- // Initialize Inputs
- K1 = 0;
- K2 = 0;
- K3 = 0;
- K4 = 0;
- RST = 0;
- CLK = 0;
- RESET = 0;
- // Wait 100 ns for global reset to finish
- #200
- RST=1;
- #100
- //przejscie do SET
- K1=1;
- K4=1;
- #100
- K1=0;
- K4=0;
- #100
- //ustawianie kodu
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- #100
- K3=1;
- #100
- K3=0;
- #100
- K4=1;
- #100
- K4=0;
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- #500
- //przejscie do wprowadzania kodu
- K2=1;
- K3=1;
- #100
- K2=0;
- K3=0;
- //kod poprawny
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- #100
- K3=1;
- #100
- K3=0;
- #100
- K4=1;
- #100
- K4=0;
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- //tu OTW
- #1000
- //powrot do stanu 1
- RESET=1;
- #100;
- RESET=0;
- #500
- //przejscie do wprowadzania kodu
- K2=1;
- K3=1;
- #200
- K2=0;
- K3=0;
- //1 bledny kod
- #300
- K2=1;
- #100
- K2=0;
- #100
- K2=1;
- #100
- K2=0;
- #100
- K3=1;
- #100
- K3=0;
- #100
- K4=1;
- #100
- K4=0;
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- //2 bledny kod
- #300
- K2=1;
- #100
- K2=0;
- #100
- K2=1;
- #100
- K2=0;
- #100
- K3=1;
- #100
- K3=0;
- #100
- K4=1;
- #100
- K4=0;
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- //3 bledny kod
- #300
- K2=1;
- #100
- K2=0;
- #100
- K2=1;
- #100
- K2=0;
- #100
- K3=1;
- #100
- K3=0;
- #100
- K4=1;
- #100
- K4=0;
- #100
- K1=1;
- #100
- K1=0;
- #100
- K2=1;
- #100
- K2=0;
- #1000
- RESET=1;
- #100;
- RESET=0;
- end
- endmodule
- *************************************
- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 14:24:31 06/20/2018
- // Design Name:
- // Module Name: debouncer
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module debouncer(input clk,
- input [3:0] PB,
- output reg [3:0] BUTTONS
- );
- reg [3:0] pb_sync;
- reg [16:0] cnt;
- always @(posedge clk)
- pb_sync<=PB;
- wire cnt_max=&cnt;
- always @(posedge clk)
- if(pb_sync==BUTTONS) cnt<=0;
- else
- begin
- cnt<=cnt+1;
- if(cnt_max) BUTTONS<=pb_sync;
- end
- endmodule
- ******************************************************
- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 20:33:18 06/18/2018
- // Design Name:
- // Module Name: zamek
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module zamek(
- input K1, K2, K3, K4,
- input RST,
- input CLK,
- input RESET,
- output reg SET,
- output reg OTW,
- output reg ALARM,
- output reg S1_LED,
- output reg WORK,
- output [5:0] _stan,
- output [2:0] _licznik
- );
- integer LICZNIK=0;
- //assign LICZNIK=0;
- reg [5:0] stan;
- reg [2:0] set_k1;
- reg [2:0] set_k2;
- reg [2:0] set_k3;
- reg [2:0] set_k4;
- reg [2:0] set_k5;
- reg [2:0] set_k6;
- reg [2:0] work_k1;
- reg [2:0] work_k2;
- reg [2:0] work_k3;
- reg [2:0] work_k4;
- reg [2:0] work_k5;
- reg [2:0] work_k6;
- wire [2:0] k1;
- wire [2:0] k2;
- wire [2:0] k3;
- wire [2:0] k4;
- debouncer db1(.clk(CLK),.PB({K1,K2,K3,K4}),.BUTTONS({k1,k2,k3,k4}));
- always@(posedge CLK)
- if(~RST) begin stan<=1; SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0; end
- else
- begin
- case(stan)
- 1: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=1; WORK<=0;
- if(K1&&K4) stan<=2;
- else if(K2&&K3) stan<=9;
- end
- 2: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k1<=3'd1; stan<=3; end
- else if(K2) begin set_k1<=3'd2; stan<=3; end
- else if(K3) begin set_k1<=3'd3; stan<=3; end
- else if(K4) begin set_k1<=3'd4; stan<=3; end
- end
- 3: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k2<=3'd1; stan<=4; end
- else if(K2) begin set_k2<=3'd2; stan<=4; end
- else if(K3) begin set_k2<=3'd3; stan<=4; end
- else if(K4) begin set_k2<=3'd4; stan<=4; end
- end
- 4: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k3<=3'd1; stan<=5; end
- else if(K2) begin set_k3<=3'd2; stan<=5; end
- else if(K3) begin set_k3<=3'd3; stan<=5; end
- else if(K4) begin set_k3<=3'd4; stan<=5; end
- end
- 5: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k4<=3'd1; stan<=6; end
- else if(K2) begin set_k4<=3'd2; stan<=6; end
- else if(K3) begin set_k4<=3'd3; stan<=6; end
- else if(K4) begin set_k4<=3'd4; stan<=6; end
- end
- 6: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k5<=3'd1; stan<=7; end
- else if(K2)begin set_k5<=3'd2; stan<=7; end
- else if(K3) begin set_k5<=3'd3; stan<=7; end
- else if(K4) begin set_k5<=3'd4; stan<=7; end
- end
- 7: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- if(K1) begin set_k6<=3'd1; stan<=8; end
- else if(K2) begin set_k6<=3'd2; stan<=8; end
- else if(K3)begin set_k6<=3'd3; stan<=8; end
- else if(K4) begin set_k6<=3'd4; stan<=8; end
- end
- 8: begin SET<=1; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=0;
- stan<=1;
- end
- 9: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k1<=3'd1; stan<=10; end
- else if(K2) begin work_k1<=3'd2; stan<=10; end
- else if(K3) begin work_k1<=3'd3; stan<=10; end
- else if(K4) begin work_k1<=3'd4; stan<=10; end
- end
- 10: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k2<=3'd1; stan<=11; end
- else if(K2) begin work_k2<=3'd2; stan<=11; end
- else if(K3) begin work_k2<=3'd3; stan<=11; end
- else if(K4) begin work_k2<=3'd4; stan<=11; end
- end
- 11: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k3<=3'd1; stan<=12; end
- else if(K2) begin work_k3<=3'd2; stan<=12; end
- else if(K3) begin work_k3<=3'd3; stan<=12; end
- else if(K4) begin work_k3<=3'd4; stan<=12; end
- end
- 12: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k4<=3'd1; stan<=13; end
- else if(K2) begin work_k4<=3'd2; stan<=13; end
- else if(K3) begin work_k4<=3'd3; stan<=13; end
- else if(K4) begin work_k4<=3'd4; stan<=13; end
- end
- 13: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k5<=3'd1; stan<=14; end
- else if(K2) begin work_k5<=3'd2; stan<=14; end
- else if(K3) begin work_k5<=3'd3; stan<=14; end
- else if(K4) begin work_k5<=3'd4; stan<=14; end
- end
- 14: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(K1) begin work_k6<=3'd1; stan<=15; end
- else if(K2) begin work_k6<=3'd2; stan<=15; end
- else if(K3) begin work_k6<=3'd3; stan<=15; end
- else if(K4) begin work_k6<=3'd4; stan<=15; end
- end
- 15: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(set_k1==work_k1&&set_k2==work_k2&&set_k3==work_k3&&set_k4==work_k4&&set_k5&&work_k5&&set_k6==work_k6) stan<=16;
- else begin LICZNIK=LICZNIK+1; stan<=17; end
- end
- 16: begin SET<=0; OTW<=1; ALARM<=0; S1_LED<=0; WORK<=0;
- if(RESET) stan<=1;
- end
- 17: begin SET<=0; OTW<=0; ALARM<=0; S1_LED<=0; WORK<=1;
- if(LICZNIK<3) stan<=9;
- else if(LICZNIK==3) begin LICZNIK=0; stan<=18; end
- end
- 18: begin SET<=0; OTW<=0; ALARM<=1; S1_LED<=0; WORK<=0;
- if(RESET) stan<=1;
- end
- endcase
- end
- assign _stan=stan;
- assign _licznik=LICZNIK;
- endmodule
- *******************************************
- NET "K4" LOC = "T16" | IOSTANDARD = LVTTL | PULLDOWN ;
- NET "K3" LOC = "T14" | IOSTANDARD = LVTTL | PULLDOWN ;
- NET "K2" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ;
- NET "K1" LOC = "U15" | IOSTANDARD = LVTTL | PULLDOWN ;
- NET "RST" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP ;
- NET "RESET" LOC = "U10"| IOSTANDARD = LVTTL | PULLUP ;
- NET "N" LOC = "T9" | IOSTANDARD = LVTTL | PULLUP ;
- NET "CLK" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
- NET "ALARM" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
- NET "OTW" LOC = "U19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
- NET "SET" LOC = "U20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
- NET "WORK" LOC = "T19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
- NET "S1_LED" LOC = "R20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
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