or1k_startup simulation

[jay@aura-R528 run]$ ./generate_bench
/home/jay/openrisc/minsoc/prj/../bench/verilog/minsoc_bench.v:301: warning: task definition for "test_uart" has an empty port declaration list!
[jay@aura-R528 run]$ ./generate_bench
/home/jay/openrisc/minsoc/prj/../bench/verilog/minsoc_bench.v:301: warning: task definition for "test_uart" has an empty port declaration list!
[jay@aura-R528 run]$ ./run_bench ../../sw/uart/uart.hex
(minsoc_bench.minsoc_top_0.uart_top) UART INFO: Data bus width is 32. Debug Interface present.

(minsoc_bench.minsoc_top_0.uart_top) UART INFO: Doesn't have baudrate output

Memory model initialized with firmware:
                                           ../../sw/uart/uart.hex
       9624 Bytes loaded from        9624 ...
Memory start-up completed...
Loaded firmware:
                                           ../../sw/uart/uart.hex
Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards.
Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)...
Hello World.
UART data received.
Testing UART interrupt...
UART interrupt working.
UART firmware test completed, behaving correctly.
Stopping simulation.