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Apr 30th, 2011
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  1.  
  2. Started : "Synthesize - XST".
  3. Running xst...
  4. Command Line: xst -intstyle ise -ifn "F:/Users/nexys2_test2/test2.xst" -ofn "F:/Users/nexys2_test2/test2.syr"
  5. Reading design: test2.prj
  6.  
  7. =========================================================================
  8. * HDL Compilation *
  9. =========================================================================
  10. Compiling verilog file "test2.v" in library work
  11. Module <hex_to_sseg> compiled
  12. Module <test2> compiled
  13. ERROR:HDLCompilers:247 - "test2.v" line 11 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  14. ERROR:HDLCompilers:44 - "test2.v" line 11 Illegal left hand side of blocking assignment
  15. ERROR:HDLCompilers:247 - "test2.v" line 12 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  16. ERROR:HDLCompilers:44 - "test2.v" line 12 Illegal left hand side of blocking assignment
  17. ERROR:HDLCompilers:247 - "test2.v" line 13 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  18. ERROR:HDLCompilers:44 - "test2.v" line 13 Illegal left hand side of blocking assignment
  19. ERROR:HDLCompilers:247 - "test2.v" line 14 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  20. ERROR:HDLCompilers:44 - "test2.v" line 14 Illegal left hand side of blocking assignment
  21. ERROR:HDLCompilers:247 - "test2.v" line 15 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  22. ERROR:HDLCompilers:44 - "test2.v" line 15 Illegal left hand side of blocking assignment
  23. ERROR:HDLCompilers:247 - "test2.v" line 16 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  24. ERROR:HDLCompilers:44 - "test2.v" line 16 Illegal left hand side of blocking assignment
  25. ERROR:HDLCompilers:247 - "test2.v" line 17 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  26. ERROR:HDLCompilers:44 - "test2.v" line 17 Illegal left hand side of blocking assignment
  27. ERROR:HDLCompilers:247 - "test2.v" line 18 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  28. ERROR:HDLCompilers:44 - "test2.v" line 18 Illegal left hand side of blocking assignment
  29. ERROR:HDLCompilers:247 - "test2.v" line 19 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  30. ERROR:HDLCompilers:44 - "test2.v" line 19 Illegal left hand side of blocking assignment
  31. ERROR:HDLCompilers:247 - "test2.v" line 20 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  32. ERROR:HDLCompilers:44 - "test2.v" line 20 Illegal left hand side of blocking assignment
  33. ERROR:HDLCompilers:247 - "test2.v" line 21 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  34. ERROR:HDLCompilers:44 - "test2.v" line 21 Illegal left hand side of blocking assignment
  35. ERROR:HDLCompilers:247 - "test2.v" line 22 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  36. ERROR:HDLCompilers:44 - "test2.v" line 22 Illegal left hand side of blocking assignment
  37. ERROR:HDLCompilers:247 - "test2.v" line 23 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  38. ERROR:HDLCompilers:44 - "test2.v" line 23 Illegal left hand side of blocking assignment
  39. ERROR:HDLCompilers:247 - "test2.v" line 24 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  40. ERROR:HDLCompilers:44 - "test2.v" line 24 Illegal left hand side of blocking assignment
  41. ERROR:HDLCompilers:247 - "test2.v" line 25 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  42. ERROR:HDLCompilers:44 - "test2.v" line 25 Illegal left hand side of blocking assignment
  43. ERROR:HDLCompilers:247 - "test2.v" line 26 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
  44. ERROR:HDLCompilers:44 - "test2.v" line 26 Illegal left hand side of blocking assignment
  45. Analysis of file <"test2.prj"> failed.
  46. -->
  47.  
  48. Total memory usage is 228316 kilobytes
  49.  
  50. Number of errors : 32 ( 0 filtered)
  51. Number of warnings : 0 ( 0 filtered)
  52. Number of infos : 0 ( 0 filtered)
  53.  
  54.  
  55. Process "Synthesize - XST" failed
RAW Paste Data

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