`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/30/2017 08:22:07 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module top(
    input clk_100mhz,
    output reg tx_hi = 1'bz,
    output reg tx_lo = 1'bz,
    output reg led = 0
    );

    wire    clk_125mhz;
    clk_wiz_0 pll
    (
        // Clock out ports
        .clk_125mhz(clk_125mhz),
        // Clock in ports
        .clk_100mhz(clk_100mhz)
    );

    //4b-5b coder
    reg[3:0] code = 0;
    reg[4:0] code_5;
    always @(*) begin
        case(code)
            0:  code_5 <= 5'b11110;
            1:  code_5 <= 5'b01001;
            2:  code_5 <= 5'b10100;
            3:  code_5 <= 5'b10101;
            4:  code_5 <= 5'b01010;
            5:  code_5 <= 5'b01011;
            6:  code_5 <= 5'b01110;
            7:  code_5 <= 5'b01111;
            8:  code_5 <= 5'b10010;
            9:  code_5 <= 5'b10011;
            10: code_5 <= 5'b10110;
            11: code_5 <= 5'b10111;
            12: code_5 <= 5'b11010;
            13: code_5 <= 5'b11011;
            14: code_5 <= 5'b11100;
            15: code_5 <= 5'b11101;
        endcase
    end

    //Bitstream generator
    reg[2:0] count = 0;
    reg txbit = 0;
    always @(posedge clk_125mhz) begin
        count   <= count + 1'h1;
        case(count)
            0:  txbit <= code_5[0];
            1:  txbit <= code_5[1];
            2:  txbit <= code_5[2];
            3:  txbit <= code_5[3];
            default: begin
                txbit <= code_5[4];
                code <= code + 1'h1;
                count <= 0;
            end
        endcase
    end

    reg[1:0] state = 0;
    always @(posedge clk_125mhz) begin
        if(txbit)
            state   <= state + 1'h1;

        //Actual output drive logic
        led     <= 1;
        case(state)
            0: begin
                tx_hi   <= 1;
                tx_lo   <= 0;
            end
            2: begin
                tx_hi   <= 0;
                tx_lo   <= 1;
            end

            default: begin
                tx_hi   <= 'bz;
                tx_lo   <= 'bz;
            end
        endcase
    end

endmodule