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- module TrafficLights_V2(clk,rst,seg_en,seg,R,Y,G);
- input clk,rst ;
- output reg R,Y,G ;
- output reg [3:0]seg_en ;
- output [6:0]seg ;
- parameter s1 = 1 ,s2 = 2 , s3 = 3 ;
- reg [1:0]state ;
- reg [30:0]div ;
- reg [7:0]count ;
- wire scan_clk ;
- reg clk_1Hz ;
- wire [3:0]scan_code ;
- always @(posedge clk or negedge rst)
- begin
- if(!rst) begin div <= 0 ; clk_1Hz <= 0 ; end
- else if(div==24999999) begin div <= 0 ; clk_1Hz <= ~clk_1Hz ; end
- else div <= div + 1 ;
- end
- assign scan_clk = div[16] ;
- //assign clk_1Hz = div[15] ;
- always @(posedge scan_clk or negedge rst)
- begin
- if(!rst) seg_en <= 4'b1110 ;
- else seg_en[3:0] <= {seg_en[0],seg_en[3:1]} ;
- end
- always @(posedge clk_1Hz or negedge rst)
- begin
- if(!rst) state <= s1 ;
- else
- case(state)
- s1:
- begin
- R = 0 ;
- if(!rst)count <= 2'h15 ;
- else if(count[3:0]==0) begin count[3:0] <= 9 ; count[7:4] <= 0 ; end
- else if(count==0) state <= s3 ;
- else count <= count - 1 ;
- end
- s2:
- begin
- Y = 0 ;
- if(!rst)count <= 2'h05 ;
- else if(count==0) state <= s1 ;
- else count <= count - 1 ;
- end
- s3:
- begin
- G = 0 ;
- if(!rst)count <= 2'h10 ;
- else if(count[3:0]==0) begin count[3:0]<=9 ; count[7:4]<=0 ; end
- else if(count==0) state <= s2 ;
- else count <= count - 1 ;
- end
- default:state <= s1 ;
- endcase
- end
- assign scan_code = (seg_en==4'b1110) ? count[3:0] :
- (seg_en==4'b1101) ? count[7:4] :
- (seg_en==4'b1011) ? count[3:0] :
- count[7:4] ;// 7's en
- assign seg[6:0] = (scan_code==4'h0) ? 7'b0000001 :
- (scan_code==4'h1) ? 7'b1001111 :
- (scan_code==4'h2) ? 7'b0010010 :
- (scan_code==4'h3) ? 7'b0000110 :
- (scan_code==4'h4) ? 7'b1001100 :
- (scan_code==4'h5) ? 7'b0100100 :
- (scan_code==4'h6) ? 7'b0100000 :
- (scan_code==4'h7) ? 7'b0001111 :
- (scan_code==4'h8) ? 7'b0000000 :
- (scan_code==4'h9) ? 7'b0000100 :
- 7'b1111111;//7's number
- endmodule
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