library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity zadatak1_tb is
end entity;

architecture Test_tb of zadatak1_tb is
	signal sDEK:std_logic_vector(7 downto 0);
	signal sF:std_logic_vector(7 downto 0);
	signal sKOMP:std_logic_vector(7 downto 0);
	signal sAS:std_logic_vector(7 downto 0);
	signal sKOD:std_logic_vector(1 downto 0);
	signal sMUX:std_logic_vector(7 downto 0);
	signal sA:std_logic_vector(2 downto 0);
	signal sB:std_logic_vector(4 downto 0);
	signal sC:std_logic_vector(7 downto 0);
	signal sSEL:std_logic_vector(3 downto 0);
	signal sRESULT:std_logic_vector(7 downto 0);

	component zadatak1 is
		port(
			iA:in std_logic_vector(2 downto 0);
			iB:in std_logic_vector(4 downto 0);
			iC:in std_logic_vector(7 downto 0);
			iSEL:in std_logic_vector(3 downto 0);
			oRESULT:out std_logic_vector(7 downto 0)
		);
	end component;

begin

	uut: zadatak1 port map(
		iA => sA,
		iB => sB,
		iC => sC,
		iSEL => sSEL,
		oRESULT => sRESULT
	);

	stimulus : process
	begin
		sA<="101";
		sB<="01100";
		sC<="01010101";
		wait for 100 ns;

		sA<="011";
		sB<="00001";
		sC<="10000000";
		wait for 100 ns;

	end process;


end architecture;