module Task2
   (
    input start,
    input [7:0] data,
    output [2:0] out
    );

    reg [7:0] d;
    reg [2:0] crc;



    assign out = crc;
    assign d = data;

 always @(posedge start)
  begin


    crc[0] = d[7] ^ d[4] ^ d[3] ^ d[2] ^ d[0];
    crc[1] = d[7] ^ d[5] ^ d[2] ^ d[1] ^ d[0];
    crc[2] = d[6] ^ d[3] ^ d[2] ^ d[1];
  end

endmodule