from artiq.experiment import *
from artiq.language.core import syscall, kernel

@syscall(flags={"nounwind", "nowrite"})
def my_csr_write(en: TInt32) -> TNone:
    raise NotImplementedError("syscall not simulated")


class SiTst(EnvExperiment):
    def build(self):
        self.setattr_device("core")

    @kernel
    def run(self):
        while 1:
            print(0)
            my_csr_write(0)
            delay(1*s)
            print(1)
            my_csr_write(1)
            delay(1*s)