module plp#(parameter addr_width=5, data_width=32)(input clk);
//program counter signals
wire [data_width-1:0] pc_0, pc, pcf, pcbranchd, pcp1f, pcp1d;
//instruction memory signals
wire [data_width-1:0] instr, instrd;
//instruction field signals
wire [5:0] opcoded, functd;
wire [4:0] shamtd,shamte;
wire [15:0] imm;
wire signed [data_width-1:0] simmd, simme;
wire [25:0] jaddr;
//register file signals
wire [4:0] rsd, rtd, rdd, rse, rte, rde, rfae, rfam, rfaw;
wire [data_width-1:0] rfrd1d, rfrd2d, rfrd1e, rfrd2e, dmdine, dmdinm;
//control unit signals
wire rfwed, mtorfseld,dmwed,branchd,aluinseld,rfdseld,jumpd,equald;
reg pcseld;
wire rfwee, mtorfsele,dmwee,aluinsele,rfdsele;
wire rfwem, mtorfselm,dmwem;
wire rfwew, mtorfselw;
wire [3:0] aluseld,alusele;
//alu signals
wire [data_width-1:0] aluin1e, aluin2e;
wire [data_width-1:0] aluoute, aluoutm, aluoutw;
//data memory signals
wire [data_width-1:0] dmoutm,dmoutw;
wire [data_width-1:0] resultw;
//hazard unit signals
wire stall, flush, forwardad, forwardbd, forwardae, forwardbe;
wire [data_width-1:0] eqld1,eqld2;

initial begin
    pcseld = 0;
end
//program counter
mux     #(.wl_1(32),.wl_0(32),.wl_out(32))  PCJMUX (.in1(pcbranchd),.in0(pcp1f),.sel(pcseld),.out(pc_0));
mux     #(.wl_1(32),.wl_0(32),.wl_out(32))  PCINMUX (.in1({pcf[31:26],jaddr}),.in0(pc_0),.sel(jumpd),.out(pc));
pl_pc   #(.width(32))                       PC    (.clk(clk), .en(stall), .pc_in(pc), .pc_out(pcf));
adder   #(.wl_1(32),.wl_2(32))              ADDR1 (.in1(pcf), .in2(1), .out(pcp1f));
adder   #(.wl_1(32),.wl_2(32))              ADDR2 (.in1(simmd<<2), .in2(pcp1d), .out(pcbranchd));

//instruction memory
pl_instr_mem #(.addr_width(8), .data_width(32)) INSTRMEM (.ima(pcf),.instr(instr));

//pipeline register - fetch/decode stage
reg_decode_data #(.width(32)) DECREG (.clk(clk),.en(stall),.clr(pcseld),.instr(instr),.pcp1f(pcp1f),.instrd(instrd),.pcp1d(pcp1d));

//instruction fields
assign opcoded = instrd[31:26];
assign rsd = instrd[25:21];
assign rtd = instrd[20:16];
assign rdd = instrd[15:11];
assign imm = instrd[15:0];
assign shamtd = instrd[10:6];
assign functd = instrd[5:0];
assign jaddr = instrd[25:0];

//sign extend
signextend SIGNEXTEND (.imm(imm),.simm(simmd));

//regiter file
pl_reg_file REGFILE (.clk(clk),.rfra1(rsd),.rfra2(rtd),.rfwa(rfaw),.rfwd(resultw),.rfwe(rfwew),.rfrd1(rfrd1d),.rfrd2(rfrd2d));

mux #(.wl_1(32),.wl_0(32),.wl_out(32)) EQLD1 (.in1(aluoutm),.in0(rfrd1d),.sel(forwardad),.out(eqld1));
mux #(.wl_1(32),.wl_0(32),.wl_out(32)) EQLD2 (.in1(aluoutm),.in0(rfrd2d),.sel(forwardbd),.out(eqld2));
assign equald = (eqld1==eqld2) ? 1:0;
always @(*) begin
    pcseld = equald & branchd;
end

//control unit
pl_control_unit PLCU (.opcode(opcoded),.funct(functd),.mtorfsel(mtorfseld), .dmwe(dmwed), .branch(branchd), .aluinsel(aluinseld), .rfdsel(rfdseld), .rfwe(rfwed), .alusel(aluseld),.jump(jumpd));

//pipeline register - decode/execute stage
reg_execute_data    EXEREG1 (.clk(clk),.clr(flush),.rfrd1d(rfrd1d),.rfrd2d(rfrd2d),.simmd(simmd),.rsd(rsd),.rtd(rtd),.rdd(rdd),.shamtd(shamtd),
                             .rfrd1e(rfrd1e),.rfrd2e(rfrd2e),.simme(simme),.rse(rse),.rte(rte),.rde(rde),.shamte(shamte));
reg_execute_signals EXEREG2 (.clk(clk),.rfwed(rfwed),.mtorfseld(mtorfseld),.dmwed(dmwed),.aluseld(aluseld),.aluinseld(aluinseld),.rfdseld(rfdseld),
                             .rfwee(rfwee),.mtorfsele(mtorfsele),.dmwee(dmwee),.alusele(alusele),.aluinsele(aluinsele),.rfdsele(rfdsele));

mux3        #(.width(32)) REGA3MUX (.in0(rfrd1e),.in1(resultw),.in2(aluoutm),.sel(forwardae),.out(aluin1e));
mux3        #(.width(32)) REGB3MUX (.in0(rfrd1e),.in1(resultw),.in2(aluoutm),.sel(forwardae),.out(dmdine));
//alu
mux         #(.width(5))  RTDMUX (.in1(rde),.in0(rte),.sel(rfdsele),.out(rfae));
mux         #(.width(32)) ALUIN2MUX (.in1(simme),.in0(dmdine),.sel(aluinsele),.out(aluin2e));
pl_alu      #(.width(32)) ALU (.aluin1(aluin1e),.aluin2(aluin2e),.shamt(shamte),.alusel(alusele),.aluout(aluoute));

//pipeline register - execute/memory stage
reg_memory_data    DATAREG1 (.clk(clk), .aluoute(aluoute), .dmdine(dmdine), .rfae(rfae),
                             .aluoutm(aluoutm), .dmdinm(dmdinm), .rfam(rfam));
reg_memory_signals DATAREG2 (.clk(clk), .rfwee(rfwee), .mtorfsele(mtorfsele), .dmwee(dmwee),
                             .rfwem(rfwem), .mtorfselm(mtorfselm), .dmwem(dmwem));

//data memory
pl_data_mem #(.addr_width(6), .data_width(32)) DATAMEM (.clk(clk),.dma(aluoutm),.dmwd(dmdinm),.dmwe(dmwem),.dmrd(dmoutm));

//pipeline register - memory/writeback stage
reg_writeback_data      WRITEREG1 (.clk(clk), .aluoutm(aluoutm), .dmoutm(dmoutm), .rtdm(rtdm), .aluoutw(aluoutw), .dmoutw(dmoutw), .rtdw(rtdw));
reg_writeback_signals   WRITEREG2 (.clk(clk), .rfwem(rfwem), .mtorfselm(mtorfselm),.rfwew(rfwew), .mtorfselw(mtorfselw));
mux         #(.wl_1(32),.wl_0(32),.wl_out(32))  DMMUX (.in1(dmoutw),.in0(aluoutw),.sel(mtorfselw),.out(resultw));

//hazard unit
pl_hazard_unit HAZARD (.branchd(branchd), .mtorfsele(mtorfsele), .mtorfselm(mtorfselm), .rfwee(rfwee), .rfwem(rfwem), .rfwew(rfwew), .jumpd(jumpd),
                       .rsd(rsd), .rtd(rtd), .rse(rse), .rte(rte), .rfae(rfae), .rfam(rfam), .rfaw(rfaw),
                       .stall(stall),
                       .flush(flush),
                       .forwardad(forwardad), .forwardbd(forwardbd),
                       .forwardae(forwardae), .forwardbe(forwardbe));

endmodule