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odroid n2 boot error - All ddr config failed... spi

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  1. $ minicom
  2.  
  3. Welcome to minicom 2.7.1
  4.  
  5. OPTIONS: I18n
  6. Compiled on May 6 2018, 08:02:47.
  7. Port /dev/ttyUSB0, 22:58:39
  8.  
  9. Press CTRL-A Z for help on special keys
  10.  
  11. G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  12. bl2_stage_init 0x01
  13. bl2_stage_init 0x81
  14. hw id: 0x0000 - pwm id 0x01
  15. bl2_stage_init 0xc1
  16. bl2_stage_init 0x02
  17.  
  18. L0:00000000
  19. L1:00000703
  20. L2:0000c067
  21. L3:14000020
  22. B2:00402000
  23. B1:e0f83180
  24.  
  25. TE: 58183
  26.  
  27. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  28.  
  29. Board ID = 4
  30. Set A53 clk to 24M
  31. Set A73 clk to 24M
  32. Set clk81 to 24M
  33. A53 clk: 1200 MHz
  34. A73 clk: 1200 MHz
  35. CLK81: 166.6M
  36. smccc: 00012b7c
  37. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  38. board id: 4
  39. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  40. fw parse done
  41. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  42. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  43. PIEI prepare done
  44. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  45. DDR4 probe
  46. ddr clk to 1320MHz
  47. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  48. Check phy result
  49. INFO : End of initialization
  50. INFO : End of read enable training
  51. INFO : End of fine write leveling
  52. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  53. INFO : STREAM 0x04020000 -
  54. INFO : ERROR : Training has failed!
  55. 1D training failed
  56. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  57. DDR4 probe
  58. ddr clk to 1320MHz
  59. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  60. Check phy result
  61. INFO : End of initialization
  62. INFO : End of read enable training
  63. INFO : End of fine write leveling
  64. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  65. INFO : STREAM 0x04020000 -
  66. INFO : ERROR : Training has failed!
  67. 1D training failed
  68. All ddr config failed...
  69. Reset...
  70. boot times 0G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  71. bl2_stage_init 0x01
  72. bl2_stage_init 0x81
  73. hw id: 0x0000 - pwm id 0x01
  74. bl2_stage_init 0xc1
  75. bl2_stage_init 0x02
  76.  
  77. L0:00000000
  78. L1:00000703
  79. L2:0000c067
  80. L3:14000020
  81. B2:00402000
  82. B1:e0f83180
  83.  
  84. TE: 58174
  85.  
  86. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  87.  
  88. Board ID = 4
  89. Set A53 clk to 24M
  90. Set A73 clk to 24M
  91. Set clk81 to 24M
  92. A53 clk: 1200 MHz
  93. A73 clk: 1200 MHz
  94. CLK81: 166.6M
  95. smccc: 00012b73
  96. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  97. board id: 4
  98. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  99. fw parse done
  100. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  101. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  102. PIEI prepare done
  103. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  104. DDR4 probe
  105. ddr clk to 1320MHz
  106. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  107. Check phy result
  108. INFO : End of initialization
  109. INFO : End of read enable training
  110. INFO : End of fine write leveling
  111. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  112. INFO : STREAM 0x04020000 -
  113. INFO : ERROR : Training has failed!
  114. 1D training failed
  115. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  116. DDR4 probe
  117. ddr clk to 1320MHz
  118. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  119. Check phy result
  120. INFO : End of initialization
  121. INFO : End of read enable training
  122. INFO : End of fine write leveling
  123. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  124. INFO : STREAM 0x04020000 -
  125. INFO : ERROR : Training has failed!
  126. 1D training failed
  127. All ddr config failed...
  128. Reset...
  129. boot times 1G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  130. bl2_stage_init 0x01
  131. bl2_stage_init 0x81
  132. hw id: 0x0000 - pwm id 0x01
  133. bl2_stage_init 0xc1
  134. bl2_stage_init 0x02
  135.  
  136. L0:00000000
  137. L1:00000703
  138. L2:0000c067
  139. L3:14000020
  140. B2:00402000
  141. B1:e0f83180
  142.  
  143. TE: 58140
  144.  
  145. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  146.  
  147. Board ID = 4
  148. Set A53 clk to 24M
  149. Set A73 clk to 24M
  150. Set clk81 to 24M
  151. A53 clk: 1200 MHz
  152. A73 clk: 1200 MHz
  153. CLK81: 166.6M
  154. smccc: 00012b50
  155. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  156. board id: 4
  157. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  158. fw parse done
  159. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  160. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  161. PIEI prepare done
  162. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  163. DDR4 probe
  164. ddr clk to 1320MHz
  165. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  166. Check phy result
  167. INFO : End of initialization
  168. INFO : End of read enable training
  169. INFO : End of fine write leveling
  170. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  171. INFO : STREAM 0x04020000 -
  172. INFO : ERROR : Training has failed!
  173. 1D training failed
  174. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  175. DDR4 probe
  176. ddr clk to 1320MHz
  177. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  178. Check phy result
  179. INFO : End of initialization
  180. INFO : End of read enable training
  181. INFO : End of fine write leveling
  182. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  183. INFO : STREAM 0x04020000 -
  184. INFO : ERROR : Training has failed!
  185. 1D training failed
  186. All ddr config failed...
  187. Reset...
  188. boot times 2G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  189. bl2_stage_init 0x01
  190. bl2_stage_init 0x81
  191. hw id: 0x0000 - pwm id 0x01
  192. bl2_stage_init 0xc1
  193. bl2_stage_init 0x02
  194.  
  195. L0:00000000
  196. L1:00000703
  197. L2:0000c067
  198. L3:14000020
  199. B2:00402000
  200. B1:e0f83180
  201.  
  202. TE: 58140
  203.  
  204. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  205.  
  206. Board ID = 4
  207. Set A53 clk to 24M
  208. Set A73 clk to 24M
  209. Set clk81 to 24M
  210. A53 clk: 1200 MHz
  211. A73 clk: 1200 MHz
  212. CLK81: 166.6M
  213. smccc: 00012b50
  214. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  215. board id: 4
  216. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  217. fw parse done
  218. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  219. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  220. PIEI prepare done
  221. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  222. DDR4 probe
  223. ddr clk to 1320MHz
  224. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  225. Check phy result
  226. INFO : End of initialization
  227. INFO : End of read enable training
  228. INFO : End of fine write leveling
  229. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  230. INFO : STREAM 0x04020000 -
  231. INFO : ERROR : Training has failed!
  232. 1D training failed
  233. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  234. DDR4 probe
  235. ddr clk to 1320MHz
  236. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  237. Check phy result
  238. INFO : End of initialization
  239. INFO : End of read enable training
  240. INFO : End of fine write leveling
  241. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  242. INFO : STREAM 0x04020000 -
  243. INFO : ERROR : Training has failed!
  244. 1D training failed
  245. All ddr config failed...
  246. Reset...
  247. boot times 3G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  248. bl2_stage_init 0x01
  249. bl2_stage_init 0x81
  250. hw id: 0x0000 - pwm id 0x01
  251. bl2_stage_init 0xc1
  252. bl2_stage_init 0x02
  253.  
  254. L0:00000000
  255. L1:00000703
  256. L2:0000c067
  257. L3:14000020
  258. B2:00402000
  259. B1:e0f83180
  260.  
  261. TE: 58140
  262.  
  263. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  264.  
  265. Board ID = 4
  266. Set A53 clk to 24M
  267. Set A73 clk to 24M
  268. Set clk81 to 24M
  269. A53 clk: 1200 MHz
  270. A73 clk: 1200 MHz
  271. CLK81: 166.6M
  272. smccc: 00012b50
  273. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  274. board id: 4
  275. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  276. fw parse done
  277. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  278. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  279. PIEI prepare done
  280. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  281. DDR4 probe
  282. ddr clk to 1320MHz
  283. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  284. Check phy result
  285. INFO : End of initialization
  286. INFO : End of read enable training
  287. INFO : End of fine write leveling
  288. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  289. INFO : STREAM 0x04020000 -
  290. INFO : ERROR : Training has failed!
  291. 1D training failed
  292. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  293. DDR4 probe
  294. ddr clk to 1320MHz
  295. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  296. Check phy result
  297. INFO : End of initialization
  298. INFO : End of read enable training
  299. INFO : End of fine write leveling
  300. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  301. INFO : STREAM 0x04020000 -
  302. INFO : ERROR : Training has failed!
  303. 1D training failed
  304. All ddr config failed...
  305. Reset...
  306. boot times 4G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  307. bl2_stage_init 0x01
  308. bl2_stage_init 0x81
  309. hw id: 0x0000 - pwm id 0x01
  310. bl2_stage_init 0xc1
  311. bl2_stage_init 0x02
  312.  
  313. L0:00000000
  314. L1:00000703
  315. L2:0000c067
  316. L3:14000020
  317. B2:00402000
  318. B1:e0f83180
  319.  
  320. TE: 58140
  321.  
  322. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  323.  
  324. Board ID = 4
  325. Set A53 clk to 24M
  326. Set A73 clk to 24M
  327. Set clk81 to 24M
  328. A53 clk: 1200 MHz
  329. A73 clk: 1200 MHz
  330. CLK81: 166.6M
  331. smccc: 00012b51
  332. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  333. board id: 4
  334. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  335. fw parse done
  336. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  337. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  338. PIEI prepare done
  339. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  340. DDR4 probe
  341. ddr clk to 1320MHz
  342. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  343. Check phy result
  344. INFO : End of initialization
  345. INFO : End of read enable training
  346. INFO : End of fine write leveling
  347. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  348. INFO : STREAM 0x04020000 -
  349. INFO : ERROR : Training has failed!
  350. 1D training failed
  351. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  352. DDR4 probe
  353. ddr clk to 1320MHz
  354. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  355. Check phy result
  356. INFO : End of initialization
  357. INFO : End of read enable training
  358. INFO : End of fine write leveling
  359. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  360. INFO : STREAM 0x04020000 -
  361. INFO : ERROR : Training has failed!
  362. 1D training failed
  363. All ddr config failed...
  364. Reset...
  365. boot times 5G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}��������с0x01
  366. bl2_stage_init 0x81
  367. hw id: 0x0000 - pwm id 0x01
  368. bl2_stage_init 0xc1
  369. bl2_stage_init 0x02
  370.  
  371. L0:00000000
  372. L1:00000703
  373. L2:0000c067
  374. L3:14000020
  375. B2:00402000
  376. B1:e0f83180
  377.  
  378. TE: 58105
  379.  
  380. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  381.  
  382. Board ID = 4
  383. Set A53 clk to 24M
  384. Set A73 clk to 24M
  385. Set clk81 to 24M
  386. A53 clk: 1200 MHz
  387. A73 clk: 1200 MHz
  388. CLK81: 166.6M
  389. smccc: 00012b2d
  390. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  391. board id: 4
  392. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  393. fw parse done
  394. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  395. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  396. PIEI prepare done
  397. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  398. DDR4 probe
  399. ddr clk to 1320MHz
  400. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  401. Check phy result
  402. INFO : End of initialization
  403. INFO : End of read enable training
  404. INFO : End of fine write leveling
  405. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  406. INFO : STREAM 0x04020000 -
  407. INFO : ERROR : Training has failed!
  408. 1D training failed
  409. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  410. DDR4 probe
  411. ddr clk to 1320MHz
  412. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  413. Check phy result
  414. INFO : End of initialization
  415. INFO : End of read enable training
  416. INFO : End of fine write leveling
  417. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  418. INFO : STREAM 0x04020000 -
  419. INFO : ERROR : Training has failed!
  420. 1D training failed
  421. All ddr config failed...
  422. Reset...
  423. boot times 6G12B:BL:6e7c85:7898ac;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}��������с0x01
  424. bl2_stage_init 0x81
  425. hw id: 0x0000 - pwm id 0x01
  426. bl2_stage_init 0xc1
  427. bl2_stage_init 0x02
  428.  
  429. L0:00000000
  430. L1:00000703
  431. L2:0000c067
  432. L3:14000020
  433. B2:00402000
  434. B1:e0f83180
  435.  
  436. TE: 58105
  437.  
  438. BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
  439.  
  440. Board ID = 4
  441. Set A53 clk to 24M
  442. Set A73 clk to 24M
  443. Set clk81 to 24M
  444. A53 clk: 1200 MHz
  445. A73 clk: 1200 MHz
  446. CLK81: 166.6M
  447. smccc: 00012b2d
  448. DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
  449. board id: 4
  450. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  451. fw parse done
  452. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  453. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  454. PIEI prepare done
  455. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  456. DDR4 probe
  457. ddr clk to 1320MHz
  458. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  459. Check phy result
  460. INFO : End of initialization
  461. INFO : End of read enable training
  462. INFO : End of fine write leveling
  463. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  464. INFO : STREAM 0x04020000 -
  465. INFO : ERROR : Training has failed!
  466. 1D training failed
  467. Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
  468. DDR4 probe
  469. ddr clk to 1320MHz
  470. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  471. Check phy result
  472. INFO : End of initialization
  473. INFO : End of read enable training
  474. INFO : End of fine write leveling
  475. INFO : STREAM 0x00490002 - 0x00000000 0x00000000
  476. INFO : STREAM 0x04020000 -
  477. INFO : ERROR : Training has failed!
  478. 1D training failed
  479. All ddr config failed...
  480. Reset...
  481. boot times 7
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