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- lowRisc SoC STRUCTURE
- ---------------------
- /----------- FIFOs (*) ----------\
- | |
- Appl.CPU0 <=>|| ||<=> Minion CPU -- (
- | || || |
- Appl.CPU1 <=>|| ||<=> Minion CPU -- S soft
- | || || |
- ... <=>||<==> DMA <==>||<=> Minion CPU -- H
- | || (**) || |
- ... <=>|| ||<=> Minion CPU -- I hardware
- || || |
- || ||<=> .... -- M )
- || || |
- || ||<=> .... ---
- || || |
- || ||<=> Minion CPU - USB + Ethernet + whatever
- || || |
- || ||<=> Minion CPU (Power, control)
- || || | +-- Flash bootrom
- || || | \-- Power and freq contr.
- || || |
- || ||<=> FPGA interface if wanted
- || || |
- L2 CACHE ||<=> Minion CPU (***)
- || | |
- TAG CACHE | | (private FIFO)
- || | |
- ||<==> DMA2 <=========> GPU (***)
- ||
- DRAM (DDR3, DDR4 or GDDR5)
- (*) Each minion has a separate two way FIFO communication channel to the
- Application CPUs. Its the Hypervisors task to prevent simultanious access.
- (**) DMA channel for each minion, programmable only by the Minion side since
- Application CPUs don't know where memory is in the Minion nor know if its
- space is free.
- (***) Open for debate on where the GPU should be positioned later on but this
- is the most logical place IMHO. The Minion can provide basic abstract settings
- like mode parameters and can pass commands/code to the GPU.
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