library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UDcounter16bit is
port ( D : in std_logic_vector(15 downto 0);
	   Resetn, LE, Dir, Clk: in std_logic;
	   Q : out std_logic_vector(15 downto 0) );
end UDcounter16bit;

architecture behavior of UDcounter16bit is
signal Qtmp : std_logic_vector(16 downto 0);
begin
	Q <= Qtmp;
	process(Clk, Resetn)
	begin
		if (Resetn = '0') then -– asynchronous reset
			Qtmp <= (others => '0');
		elsif (Clk'event and Clk = '1') then
			if (LE = '1') then Qtmp <= D -- load value
			else
				case Dir is
					when '0' => –- count up
						Qtmp <= Qtmp + 1;
					when '1' => –- count down
						Qtmp <= Qtmp - 1;
					when others => Qtmp <= Qtmp;
				end case;
			end if;
		end if;
	end process;
end behavior;