pin muxing for /bone/uart/1 - 6/18/20

For /bone/uart/1


BBAI: We have to set 9 pin configurations to achieve /bone/uart/1 on BBAI with rts and cts

	bb_uart10_pins: pinmux_bb_uart10_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(BBAI_P9_24, PIN_OUTPUT_PULLUP | MUX_MODE3)	/* gpio6_15.uart10_txd */
			DRA7XX_CORE_IOPAD(BBAI_P9_26A, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpio6_14.uart10_rxd */
			/* unused pins */
			DRA7XX_CORE_IOPAD(BBAI_P9_26B, PIN_OUTPUT | MUX_MODE15)

			/* comment these pins in cape_pins_default and uncomment here to use*/
			// DRA7XX_CORE_IOPAD(BBAI_P9_19B, PIN_OUTPUT | MUX_MODE8)	/* vin2a_d5.uart10_rtsn */
			// DRA7XX_CORE_IOPAD(BBAI_P9_20B, PIN_INPUT | MUX_MODE8)	/* vin2a_d4.uart10_ctsn */
			// DRA7XX_CORE_IOPAD(BBAI_P8_04, PIN_OUTPUT | MUX_MODE8)	/* mmc3_dat7.uart10_rtsn */
			// DRA7XX_CORE_IOPAD(BBAI_P8_03, PIN_INPUT | MUX_MODE8)		/* mmc3_dat6.uart10_ctsn */
			/* unused pins */
			// DRA7XX_CORE_IOPAD(BBAI_P9_19A, PIN_OUTPUT | MUX_MODE15)
			// DRA7XX_CORE_IOPAD(BBAI_P9_20A, PIN_OUTPUT | MUX_MODE15)
		>;
	};


BBB: We have to set 4 pin configurations to achieve /bone/uart/1 on BBB with rts and cts

	bb_uart1_pins: pinmux_bb_uart1_pins {
		pinctrl-single,pins = <
			BONE_P9_24 (PIN_OUTPUT | MUX_MODE0)	// uart1_txd.uart1_txd
			BONE_P9_26 (PIN_INPUT | MUX_MODE0)	// uart1_rxd.uart1_rxd
			//	BONE_P9_19 (PIN_OUTPUT | MUX_MODE0)	// uart1_rtsn.uart1_rtsn
			//	BONE_P9_20 (PIN_INPUT | MUX_MODE0)	// uart1_ctsn.uart1_ctsn
		>;
	};