set ssram_tco_min 1
set ssram_tco_max 3
set ssram_tsu 1.4
set ssram_th 0.4

set_input_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay -$ssram_th [get_ports {ssram_data[*]}]
set_input_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tsu [get_ports {ssram_data[*]}]

set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_a_0[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_a_0[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_bw_0[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_bw_0[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_data[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_data[*]}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_cen_0}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_cen_0}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_oen_0}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_oen_0}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -min -add_delay $ssram_tco_min [get_ports {ssram_wn_0}]
set_output_delay -clock [get_clocks {SSRAM_CL}] -max -add_delay $ssram_tco_max [get_ports {ssram_wn_0}]