//Matrix multipication: 3X3 , each elements is 8-bits wide
//Upon exiting reset mode the module executes mat_c=mat_a X mat_b

module matrix_mul(clk,rstn,a,b,c,done);
//Input declerations
input logic clk;
input logic rstn;
input logic signed [71:0] a;
input logic signed [71:0] b;

//Output declerations
output logic done;
output logic signed [71:0] c;

//Internal signals
integer i,j,k;                          //Used in for loops
logic first_cycle;                      //Indicates initiation of a multiplication procedure
logic done;                             //Rises to logic high when result is ready to be transformed into 1D form

logic signed [7:0] mat_a [2:0][2:0];    //Internal 2D representation of the 72-bit input vector a
logic signed [7:0] mat_b [2:0][2:0];    //Internal 2D representation of the 72-bit input vector b
logic signed [7:0] mat_c [2:0][2:0];    //Internal 2D representation of the resulting matrix, i.e. 3X3 matrix with each cell comprising 8 bits

//HDL code

always @(posedge clk or negedge rstn)
  if (!rstn) begin
    first_cycle<=1'b1;
    done<=1'b0;
    for (i=0; i<3; i=i+1)
      for (j=0; j<3 ;j=j+1) begin
        mat_a[i][j]<='0;
        mat_b[i][j]<='0;
        mat_c[i][j]<='0;
      end
  end
  else if (first_cycle) begin                              //1D->2D
    for (i=0; i<3; i=i+1)
      for (j=0; j<3; j=j+1) begin
        mat_a[i][j]<=a[(3*i+j)*8:+8];
        mat_b[i][j]<=b[(3*i+j)*8:+8];
        mat_c[i][j]<='0;
      end
    first_cycle<=1'b0;
  end
  else if (!done) begin                                   //Execute the matrix multipication
    for (i=0;i<3; i=i+1)
      for (j=0; j<3; j=j+1)
        for (k=0; k<3; k=k+1)
          mat_c[i][j]<=mat_c[i][j]+mat_a[i][k]*mat_b[k][j];
    done<=1'b1;
  end
  else if (done) begin                                    //2D->1D
    for (i=0; i<3; i=i+1)
      for (j=0; j<3; j=j+1) begin
        c[(3*i+j)*8+:8]<=mat_c[i][j];
      end
  end

endmodule