library ieee;
library lab2a;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity lab_3 is
Port ( SMAR: in bit;
		 SMBR: in bit;
		 WR: in bit;
		 RD: in bit;
		 A: in std_logic_vector(32 downto 1);
		 DO: in std_logic_vector(16 downto 1);
		 D: inout std_logic_vector(16 downto 1);
		 AD: out std_logic_vector(32 downto 1);
		 HEX1 : OUT STD_LOGIC_VECTOR(7 downto 1);
		 HEX2 : OUT STD_LOGIC_VECTOR(7 downto 1);
		 DI: out std_logic_vector(16 downto 1);
		 BU : BUFFER std_logic_vector(32 downto 1);
		 WROUT: out bit;
		 RDOUT: out bit;
		 SMAROUT: out bit;
		 SMBROUT: out bit);
end lab_3;

architecture beh of lab_3 is

component lab2a is
    port( i : in STD_LOGIC_VECTOR(3 downto 0);
			 HEX0 : OUT STD_LOGIC_VECTOR(6 downto 0));
end component;

signal MAR: std_logic_vector(16 downto 1);
signal MBR: std_logic_vector(16 downto 1);
signal OCB: std_logic_vector(32 downto 1);
begin

process(SMAR,A,SMBR,DO,WR,RD)
begin

if(SMAR = '1') then BU<=A; --na wyjscie jest A, jesli nie 1 to pamieta
	end if;

if(SMBR ='1') then D<=DO; --na wyjscie jest DO, jesli nie 1 to pamieta
	end if;

if(WR = '0') then D<="ZZZZZZZZZZZZZZZZ"; --na wyjscie jest
	elsif (WR ='1') then D<=MBR; --na wyjscie jest MBR
	end if;

	if(RD = '1') then MBR<=D; --na wyjscie jest D, jesli nie 1 to pamieta
	end if;

	 -- przeslanie danych na wyjscie
	AD<=BU;
	SMAROUT<=SMAR;
	SMBROUT<=SMBR;
	WROUT<=WR;
	RDOUT<=RD;
end process;

Gate: lab2a port map(i =>BU(4 downto 1)  , HEX0=>HEX1);
Gate1: lab2a port map(i =>D(4 downto 1)  , HEX0=>HEX2);

end beh;