module read_flash_fsm ( input logic clk,
								input logic start,
								input logic[21:0] in_addr,
								input logic[7:0] flash_data,
								output logic finish,
								output logic[21:0] out_addr,
								output logic out_CE_N,
								output logic out_OE_N,
								output logic[15:0] audio_data );

	// State Encoding = {State Number, finish, out_CE_N, out_OE_N}
	parameter WAIT_FOR_FIRST_BYTE 	= 6'b000_011;
	parameter OUTPUT_TO_FLASH 			= 6'b001_000;
	parameter REGISTER_DATA				= 6'b010_011;
	parameter WAIT_FOR_SECOND_BYTE 	= 6'b011_111;
	parameter OUTPUT_FINISH				= 6'b111_111;

	reg[5:0] state;
	wire sample_collected;

	// FSM
	always_ff @ (posedge clk) begin
		case (state)

			WAIT_FOR_FIRST_BYTE : if (start) state <= OUTPUT_TO_FLASH;

			OUTPUT_TO_FLASH : state <= REGISTER_DATA;

			REGISTER_DATA : if (sample_collected) begin
									state <= OUTPUT_FINISH;
									audio_data[15:8] = flash_data;
									sample_collected <= 1'b0;
								 end
								 else begin
									state <= WAIT_FOR_SECOND_BYTE;
									audio_data[7:0] = flash_data;
									sample_collected <= 1'b1;
								 end

			WAIT_FOR_SECOND_BYTE : if (start) state <= OUTPUT_TO_FLASH;

			OUTPUT_FINISH : begin
										state <= WAIT_FOR_FIRST_BYTE;
										audio_data = 16'b0;
								 end
			default : state <= WAIT_FOR_FIRST_BYTE;
		endcase
	end

	assign out_addr = in_addr;
	assign finish = state[2];
	assign out_CE_N = state[1];
	assign out_OE_N = state[0];

endmodule