module Lab7Part2(
    	 input [9:0]SW,
	 input [3:0]KEY,
	 input CLOCK_50,
	 output [6:0]X,
	 output [6:0]Y,
	 output [2:0]color
);
wire loadx,loady,ld_draw,ld_clear;
wire [4:0]counter;
wire [7:0]clear;


control b1(
				.clk(CLOCK_50),
				.resetn(KEY[0]),
				.KEY3(KEY[3]),
				.KEY1(KEY[1]),
				.KEY2(KEY[2]),
				.loadx(loadx),
				.loady(loady),
				.ld_draw(ld_draw),
				.ld_clear(ld_clear),
				.counter(counter),
				.clear(clear)
	);
datapath b2(
				.clk(CLOCK_50),
				.resetn(KEY[0]),
				.datain(SW[9:0]),
				.loadx(loadx),
				.loady(loady),
				.ld_draw(ld_draw),
				.ld_clear(ld_clear),
				.X(X),
				.Y(Y),
				.color(color),
				.counter(counter),
				.clear(clear)
	);
endmodule

module control(
    	 input clk,
    	 input resetn,
    	 input KEY3,
	 input KEY1,
	 input KEY2,
    	 output reg  loadx,loady,ld_draw,ld_clear,
    	 input [4:0]counter,
	 input [7:0]clear
    );

    reg [5:0] current_state, next_state;

    localparam  S_LOAD_X        = 5'd0,
                S_LOAD_X_Wait   = 5'd1,
                S_LOAD_Y        = 5'd2,
                S_LOAD_Y_Wait   = 5'd3,
                drawstate       = 5'd4,
		clearstate      = 5'd5;



 always@(*)
    begin: state_table
            case (current_state)
                S_LOAD_X: next_state = KEY3 ? S_LOAD_X_Wait : S_LOAD_X;
		S_LOAD_X_Wait : next_state = KEY3 ? S_LOAD_X_Wait : S_LOAD_Y;
		S_LOAD_Y: next_state = KEY1 ? S_LOAD_Y_Wait : S_LOAD_Y;
		S_LOAD_Y_Wait: next_state = KEY1 ? S_LOAD_Y_Wait : drawstate;
		drawstate: next_state = ((counter == 5'b10000)? S_LOAD_X : drawstate);
		clearstate: next_state = ((clear == 8'b10000000)? S_LOAD_X : clearstate);
            default: next_state = S_LOAD_X;
        endcase
    end // state_table



	// Output logic aka all of our datapath control signals
    always @(*)
    begin: enable_signals
        loadx = 1'b0;
        loady = 1'b0;
	ld_draw = 1'b0;
	ld_clear =1'b0;

        case (current_state)
            S_LOAD_X: begin
                loadx = 1'b1;
                end
            S_LOAD_Y: begin
                loady = 1'b1;
                end
			drawstate: begin
				ld_draw = 1'b1;
				   end
			clearstate: begin
				ld_clear = 1'b1;
				    end
        endcase
    end

	// current_state registers

  always@(posedge clk)
    begin: state_FFs
        if(!resetn)
            current_state <= S_LOAD_X;
		  if(KEY2)
			current_state <= clearstate;
        else
            current_state <= next_state;
    end

endmodule




module datapath(
    	 input clk,
    	 input resetn,
    	 input [9:0] datain,
    	 input loadx,loady,ld_draw,ld_clear,
    	 output reg[6:0]X,
    	 output reg[6:0]Y,
    	 output reg[2:0]color,
    	 output reg [4:0]counter,
    	 output reg[7:0]clear
    );
         reg [6:0]Xdraw;
	 reg [6:0]Ydraw;
	 reg [6:0]Xclear;
	 reg [6:0]Yclear;
	 reg [6:0]Xo;
	 reg [6:0]Yo;


	always@(posedge clk) begin
        if(!resetn) begin
			Xo <= 7'b0;
			Yo <= 7'b0;
        end
        else begin

            if(loadx)
			Xo <= datain[6:0];
            if(loady)
			Yo <= datain[6:0];
        end
    end


	  always@(posedge clk)
			begin
				if(!resetn)
				begin
				Xclear <= 7'b0;
				Yclear <= 7'b0;
				clear <= 8'b00000000;
				end

				else
				begin
				if(ld_clear && (clear != 8'b10000000))
					begin
						Xclear <= 0 + clear;
						Yclear <= 0 + clear;
						clear <= clear + 1;
					end
				if(!ld_clear)
					begin
						 clear <= 8'b00000000;
					end
				end
			end

	  always@(posedge clk)
			begin
				if(!resetn) begin
				Xdraw<=7'b0;
				Ydraw<=7'b0;
				end
				else
				begin
				if(ld_draw && (counter != 5'b10000))
					begin
						Xdraw <= Xo + counter[1:0];
						Ydraw <= Yo + counter[3:2];
						counter <= counter + 1;
					end
				else
					begin
						if(!ld_draw)
							  begin
								 counter <= 5'b00000;
								 Xdraw <= Xo;
								 Ydraw <= Yo;
						  end
					end
				end
			end

		 always@(posedge clk) begin
        if(!resetn) begin
           X <= 7'b0;
			  Y <= 7'b0;
			  color <= 3'b0;
        end
        else
           begin
					  if(ld_draw)
							 begin
							 X <= Xdraw;
							 Y <= Ydraw;
							 color <= datain[9:7];
							 end
						if(ld_clear)
							 begin
							 X <= Xclear;
							 Y <= Yclear;
							 color <= 3'b000;
							 end
            end
		end
endmodule