mult_signed_clk.v

module mult_signed_clk(in1, in2, clk, out);
   input signed [3:0] in1;
   input signed [3:0] in2;
   output signed [4:0] out;
   input       clk;

   reg signed [4:0]   out;

   always @(posedge clk)
     begin
        out = in1*in2;
     end

endmodule