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dc_dmub_srv regression

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Aug 28th, 2022
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  1. [17:37:28] Starting KUnit Kernel (1/1)...
  2. [17:37:28] ============================================================
  3. Running tests with:
  4. $ qemu-system-x86_64 -nodefaults -m 1024 -kernel .kunit/arch/x86/boot/bzImage -append 'mem=1G console=tty kunit_shutdown=halt console=ttyS0 kunit_shutdown=reboot' -no-reboot -nographic -serial stdio
  5. [17:37:28] ============= dml_calcs_bw_fixed (6 subtests) ==============
  6. [17:37:28] [PASSED] abs_i64_test
  7. [17:37:28] [PASSED] bw_int_to_fixed_nonconst_test
  8. [17:37:28] [PASSED] bw_frc_to_fixed_test
  9. [17:37:28] [PASSED] bw_floor2_test
  10. [17:37:28] [PASSED] bw_ceil2_test
  11. [17:37:28] [PASSED] bw_mul_test
  12. [17:37:28] =============== [PASSED] dml_calcs_bw_fixed ================
  13. [17:37:28] =========== display_rq_dlg_calc_20 (3 subtests) ============
  14. [17:37:28] [PASSED] get_bytes_per_element_test
  15. [17:37:28] [PASSED] is_dual_plane_test
  16. [17:37:28] [PASSED] get_blk_size_bytes_test
  17. [17:37:28] ============= [PASSED] display_rq_dlg_calc_20 ==============
  18. [17:37:28] ============= display_mode_vba_20 (6 subtests) =============
  19. [17:37:28] [PASSED] dscce_compute_delay_test
  20. [17:37:28] [PASSED] DSC_compute_delay_test
  21. [17:37:28] [PASSED] calculate_TWait_test
  22. [17:37:28] ============= calculate_write_back_delay_test ==============
  23. [17:37:28] [PASSED] Trivial test
  24. [17:37:28] [PASSED] High Writeback HRatio and VRatio and zeroed taps
  25. [17:37:28] [PASSED] Simple Writeback Ratio
  26. [17:37:28] [PASSED] Non-integer WritebackVRatio with same number of Luma and Chroma taps
  27. [17:37:28] [PASSED] No Writeback to Chroma Taps
  28. [17:37:28] [PASSED] No Writeback to Luma Taps
  29. [17:37:28] [PASSED] High Writeback HRatio and VRatio
  30. [17:37:28] [PASSED] Increase numeric error by increasing taps' Writeback
  31. [17:37:28] [PASSED] Turning point of the Writeback HRatio and VRatio
  32. [17:37:28] [PASSED] Simple Writeback Ratio for 4:4:4 8-bit encoding
  33. [17:37:28] [PASSED] Non-integer WritebackVRatio with same number of Luma and Chroma taps for 4:4:4 64-bit encoding
  34. [17:37:28] [PASSED] No Writeback to Chroma Taps for 4:2:0 8-bit encoding
  35. [17:37:28] [PASSED] No Writeback to Luma Taps for 4:2:0 10-bit encoding
  36. [17:37:28] [PASSED] Reduce numeric error by decreasing Writeback HRatio and VRatio for 4:4:4 16-bit encoding
  37. [17:37:28] ========= [PASSED] calculate_write_back_delay_test =========
  38. [17:37:28] =========== calculate_active_row_bandwidth_test ============
  39. [17:37:28] [PASSED] Trivial Test
  40. [17:37:28] [PASSED] Zeroed Bandwidth with non-zeroed values
  41. [17:37:28] [PASSED] GPUVM enabled and DCC not enabled with 4:2:0 8-bit encoding
  42. [17:37:28] [PASSED] GPUVM enabled and DCC not enabled with 4:2:0 10-bit encoding
  43. [17:37:28] [PASSED] GPUVM enabled and DCC not enabled with 4:2:0 12-bit encoding
  44. [17:37:28] [PASSED] GPUVM enabled and DCC not enabled with 4:4:4 16-bit encoding
  45. [17:37:28] [PASSED] GPUVM not enabled and DCC enabled with 4:2:0 8-bit encoding
  46. [17:37:28] [PASSED] GPUVM not enabled and DCC enabled with 4:2:0 10-bit encoding
  47. [17:37:28] [PASSED] GPUVM not enabled and DCC enabled with 4:2:2 8-bit encoding
  48. [17:37:28] [PASSED] GPUVM not enabled and DCC enabled with 4:4:4 8-bit encoding
  49. [17:37:28] [PASSED] GPUVM enabled and DCC enabled with 4:2:0 8-bit encoding
  50. [17:37:28] [PASSED] GPUVM enabled and DCC enabled with 4:2:0 10-bit encoding
  51. [17:37:28] [PASSED] GPUVM enabled and DCC enabled with 4:4:4 16-bit encoding
  52. [17:37:28] [PASSED] GPUVM enabled and DCC enabled with 4:4:4 32-bit encoding
  53. [17:37:28] ======= [PASSED] calculate_active_row_bandwidth_test =======
  54. [17:37:28] [PASSED] trunc_to_valid_BPP_test
  55. [17:37:28] =============== [PASSED] display_mode_vba_20 ===============
  56. [17:37:28] ================= dc_dmub_srv (1 subtest) ==================
  57. [17:37:28] ============= populate_subvp_cmd_drr_info_test =============
  58. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:269
  59. [17:37:28] Expected test_param->min_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported, but
  60. [17:37:28] test_param->min_vtotal_supported == 63709
  61. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported == 0
  62. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:271
  63. [17:37:28] Expected test_param->max_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported, but
  64. [17:37:28] test_param->max_vtotal_supported == 363
  65. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported == 0
  66. [17:37:28] not ok 1 - Same Clock Frequency
  67. [17:37:28] [FAILED] Same Clock Frequency
  68. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:269
  69. [17:37:28] Expected test_param->min_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported, but
  70. [17:37:28] test_param->min_vtotal_supported == 63709
  71. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported == 0
  72. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:271
  73. [17:37:28] Expected test_param->max_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported, but
  74. [17:37:28] test_param->max_vtotal_supported == 346
  75. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported == 0
  76. [17:37:28] not ok 2 - Same Clock Frequency with Prefetch End to Mall Start
  77. [17:37:28] [FAILED] Same Clock Frequency with Prefetch End to Mall Start
  78. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:269
  79. [17:37:28] Expected test_param->min_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported, but
  80. [17:37:28] test_param->min_vtotal_supported == 1387
  81. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported == 0
  82. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:271
  83. [17:37:28] Expected test_param->max_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported, but
  84. [17:37:28] test_param->max_vtotal_supported == 399
  85. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported == 0
  86. [17:37:28] not ok 3 - Same Clock Frequency Not Multiple of 2
  87. [17:37:28] [FAILED] Same Clock Frequency Not Multiple of 2
  88. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:269
  89. [17:37:28] Expected test_param->min_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported, but
  90. [17:37:28] test_param->min_vtotal_supported == 1477
  91. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported == 0
  92. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:271
  93. [17:37:28] Expected test_param->max_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported, but
  94. [17:37:28] test_param->max_vtotal_supported == 212
  95. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported == 0
  96. [17:37:28] not ok 4 - Different Clock Frequency for smaller h_total and v_total
  97. [17:37:28] [FAILED] Different Clock Frequency for smaller h_total and v_total
  98. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:269
  99. [17:37:28] Expected test_param->min_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported, but
  100. [17:37:28] test_param->min_vtotal_supported == 2482
  101. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported == 0
  102. [17:37:28] # populate_subvp_cmd_drr_info_test: EXPECTATION FAILED at drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:271
  103. [17:37:28] Expected test_param->max_vtotal_supported == pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported, but
  104. [17:37:28] test_param->max_vtotal_supported == 247
  105. [17:37:28] pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported == 0
  106. [17:37:28] not ok 5 - Different Clock Frequency for approximately 1920x1080
  107. [17:37:28] [FAILED] Different Clock Frequency for approximately 1920x1080
  108. [17:37:28] # Subtest: populate_subvp_cmd_drr_info_test
  109. [17:37:28] # populate_subvp_cmd_drr_info_test: pass:0 fail:5 skip:0 total:5
  110. [17:37:28] not ok 1 - populate_subvp_cmd_drr_info_test
  111. [17:37:28] ======== [FAILED] populate_subvp_cmd_drr_info_test =========
  112. [17:37:28] # Subtest: dc_dmub_srv
  113. [17:37:28] 1..1
  114. [17:37:28] # Totals: pass:0 fail:5 skip:0 total:5
  115. [17:37:28] not ok 4 - dc_dmub_srv
  116. [17:37:28] =================== [FAILED] dc_dmub_srv ===================
  117. [17:37:28] ============ dc_basics_fixpt31_32 (5 subtests) =============
  118. [17:37:28] [PASSED] dc_fixpt_from_int_test
  119. [17:37:28] [PASSED] dc_fixpt_from_fraction_test
  120. [17:37:28] [PASSED] dc_fixpt_mul_test
  121. [17:37:28] [PASSED] dc_fixpt_sqr_test
  122. [17:37:28] [PASSED] dc_fixpt_recip_test
  123. [17:37:28] ============== [PASSED] dc_basics_fixpt31_32 ===============
  124. [17:37:28] ============ dml_display_mode_vba (4 subtests) =============
  125. [17:37:28] == pclk_adjustment_for_progressive_to_interlace_unit_test ==
  126. [17:37:28] [PASSED] No active planes
  127. [17:37:28] [PASSED] Two active planes with no interlaced output
  128. [17:37:28] [PASSED] Three active planes with one interlaced plane
  129. [17:37:28] [PASSED] Five active planes with three interlaced planes
  130. [17:37:28] [PASSED] Eight active planes with five interlaced planes
  131. [17:37:28] [PASSED] Eight active planes with all planes interlaced
  132. [17:37:28] [PASSED] Eight active planes with no interlaced plane
  133. [17:37:28] [PASSED] Eight active planes with no progressive_to_interlace_unit_in_OPP
  134. [17:37:28] === [PASSED] pclk_adjustment_for_progressive_to_interlace_unit_test ===
  135. [17:37:28] ============= calculate_256B_block_sizes_test ==============
  136. [17:37:28] [PASSED] 4:4:4 16-bit encoding with linear swizzle
  137. [17:37:28] [PASSED] 4:4:4 16-bit encoding with 256B standard swizzle
  138. [17:37:28] [PASSED] 4:4:4 32-bit encoding with linear swizzle
  139. [17:37:28] [PASSED] 4:4:4 32-bit encoding with 256B display swizzle
  140. [17:37:28] [PASSED] 4:4:4 64-bit encoding with linear swizzle
  141. [17:37:28] [PASSED] 4:4:4 64-bit encoding with 4KB standard swizzle
  142. [17:37:28] [PASSED] 4:4:4 8-bit encoding with linear swizzle
  143. [17:37:28] [PASSED] 4:4:4 8-bit encoding with 4KB display swizzle
  144. [17:37:28] [PASSED] 8-bit mono encoding with linear swizzle
  145. [17:37:28] [PASSED] 8-bit mono encoding with 64KB standard swizzle
  146. [17:37:28] [PASSED] 16-bit mono encoding with linear swizzle
  147. [17:37:28] [PASSED] 16-bit mono encoding with 64KB display swizzle
  148. [17:37:28] [PASSED] 8-bit 4:2:0 encoding with linear swizzle
  149. [17:37:28] [PASSED] 8-bit 4:2:0 encoding with VAR standard swizzle
  150. [17:37:28] [PASSED] 10-bit 4:2:0 encoding with linear swizzle
  151. [17:37:28] [PASSED] 10-bit 4:2:0 encoding with VAR display swizzle
  152. [17:37:28] ========= [PASSED] calculate_256B_block_sizes_test =========
  153. [17:37:28] [PASSED] calculate_min_and_max_prefetch_mode_test
  154. [17:37:28] ============ calculate_write_back_DISPCLK_test =============
  155. [17:37:28] [PASSED] Trivial test
  156. [17:37:28] [PASSED] Simple Writeback Ratio
  157. [17:37:28] [PASSED] Non-integer WritebackVRatio with same number of Luma and Chroma taps
  158. [17:37:28] [PASSED] No Writeback to Chroma Taps
  159. [17:37:28] [PASSED] No Writeback to Luma Taps
  160. [17:37:28] [PASSED] Reduce numeric error by decreasing pixel clock
  161. [17:37:28] [PASSED] Increase numeric error by increasing pixel clock
  162. [17:37:28] [PASSED] Simple Writeback Ratio for 4:4:4 8-bit encoding
  163. [17:37:28] [PASSED] Non-integer WritebackVRatio with same number of Luma and Chroma taps for 4:4:4 64-bit encoding
  164. [17:37:28] [PASSED] No Writeback to Chroma Taps for 4:2:0 8-bit encoding
  165. [17:37:28] [PASSED] No Writeback to Luma Taps for 4:2:0 10-bit encoding
  166. [17:37:28] [PASSED] Reduce numeric error by decreasing pixel clock for 4:4:4 16-bit encoding
  167. [17:37:28] [PASSED] Increase numeric error by increasing pixel clock for 4:4:4 16-bit encoding
  168. [17:37:28] ======== [PASSED] calculate_write_back_DISPCLK_test ========
  169. [17:37:28] ============== [PASSED] dml_display_mode_vba ===============
  170. [17:37:28] ================ dml_dcn20_fpu (1 subtest) =================
  171. [17:37:28] ================ dcn20_cap_soc_clocks_test =================
  172. [17:37:28] [PASSED] 4-state bounding box clock limits
  173. [17:37:28] [PASSED] One duplicate clock state
  174. [17:37:28] [PASSED] Zeroed max clocks
  175. [17:37:28] ============ [PASSED] dcn20_cap_soc_clocks_test ============
  176. [17:37:28] ================== [PASSED] dml_dcn20_fpu ==================
  177. [17:37:28] === dml_dcn20_fpu_dcn21_update_bw_bounding_box_test (1 subtest) ===
  178. [17:37:28] ============ dcn21_update_bw_bounding_box_test =============
  179. [17:37:28] [PASSED] 5-entry bounding box clocks table
  180. [17:37:28] ======== [PASSED] dcn21_update_bw_bounding_box_test ========
  181. [17:37:28] = [PASSED] dml_dcn20_fpu_dcn21_update_bw_bounding_box_test =
  182. [17:37:28] ============================================================
  183. [17:37:28] Testing complete. Passed: 88, Failed: 5, Crashed: 0, Skipped: 0, Errors: 0
  184. [17:37:29] Elapsed time: 62.794s total, 0.004s configuring, 61.321s building, 0.841s running
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