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  1. coreboot-4.10-854-g3d4923d85a-2.0-beta2 Wed Oct 2 11:26:53 UTC 2019 bootblock starting (log level: 7)...
  2. CPU: Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz
  3. CPU: ID 406e3, Skylake D0, ucode: 000000cb
  4. CPU: AES supported, TXT NOT supported, VT supported
  5. MCH: device id 1904 (rev 08) is Skylake-U
  6. PCH: device id 9d48 (rev 21) is Skylake-U Premium
  7. IGD: device id 1916 (rev 07) is Skylake ULT GT2
  8. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  9. CBFS: Locating 'fallback/romstage'
  10. CBFS: Found @ offset 80 size b5ec
  11.  
  12.  
  13. coreboot-4.10-854-g3d4923d85a-2.0-beta2 Wed Oct 2 11:26:53 UTC 2019 romstage starting (log level: 7)...
  14. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00
  15. gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  16. gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  17. gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  18. gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
  19. TCO_STS: 0000 0000
  20. GEN_PMCON: a0040200 0000500b
  21. GBLRST_CAUSE: 00000000 00000000
  22. prev_sleep_state 5
  23. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  24. CBFS: Locating 'fspm.bin'
  25. CBFS: Found @ offset 2adc0 size 63000
  26. FMAP: area RW_MRC_CACHE found @ 270000 (65536 bytes)
  27. MRC: no data in 'RW_MRC_CACHE'
  28. SPD @ 0x50
  29. SPD: module type is DDR4
  30. SPD: module part is HMA41GS6AFR8N-TF
  31. SPD: banks 16, ranks 2, rows 15, columns 10, density 4096 Mb
  32. SPD: device width 8 bits, bus width 64 bits
  33. SPD: module size is 8192 MB (per channel)
  34. SPD @ 0x52
  35. SPD: module type is DDR4
  36. SPD: module part is HMA41GS6AFR8N-TF
  37. SPD: banks 16, ranks 2, rows 15, columns 10, density 4096 Mb
  38. SPD: device width 8 bits, bus width 64 bits
  39. SPD: module size is 8192 MB (per channel)
  40. CBMEM:
  41. IMD: root @ 7affe000 254 entries.
  42. IMD: root @ 7affdc00 62 entries.
  43. External stage cache:
  44. IMD: root @ 7b3ff000 254 entries.
  45. IMD: root @ 7b3fec00 62 entries.
  46. 2 DIMMs found
  47. SMM Memory Map
  48. SMRAM : 0x7b000000 0x800000
  49. Subregion 0: 0x7b000000 0x200000
  50. Subregion 1: 0x7b200000 0x200000
  51. Subregion 2: 0x7b400000 0x400000
  52. top_of_ram = 0x7afff000
  53. MTRR Range: Start=79fff000 End=7a000000 (Size 1000)
  54. MTRR Range: Start=7a000000 End=7a800000 (Size 800000)
  55. MTRR Range: Start=7a800000 End=7ac00000 (Size 400000)
  56. MTRR Range: Start=7ac00000 End=7ae00000 (Size 200000)
  57. MTRR Range: Start=7ae00000 End=7af00000 (Size 100000)
  58. MTRR Range: Start=7af00000 End=7af80000 (Size 80000)
  59. MTRR Range: Start=7af80000 End=7afc0000 (Size 40000)
  60. MTRR Range: Start=7afc0000 End=7afe0000 (Size 20000)
  61. MTRR Range: Start=7afe0000 End=7aff0000 (Size 10000)
  62. MTRR Range: Start=7aff0000 End=7aff8000 (Size 8000)
  63. No more variable MTRRs: 10
  64. No more variable MTRRs: 10
  65. No more variable MTRRs: 10
  66. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  67. CBFS: Locating 'fallback/postcar'
  68. CBFS: Found @ offset cce80 size 8a8c
  69. Decompressing stage fallback/postcar @ 0x7abcbfc0 (50584 bytes)
  70. Loading module at 7abcc000 with entry 7abcc000. filesize: 0x8190 memsize: 0xc558
  71. Processing 552 relocs. Offset value of 0x78bcc000
  72.  
  73.  
  74. coreboot-4.10-854-g3d4923d85a-2.0-beta2 Wed Oct 2 11:26:53 UTC 2019 postcar starting (log level: 7)...
  75. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  76. CBFS: Locating 'fallback/ramstage'
  77. CBFS: Found @ offset b700 size 1e6c0
  78. Decompressing stage fallback/ramstage @ 0x7aafbfc0 (845720 bytes)
  79. Loading module at 7aafc000 with entry 7aafc000. filesize: 0x41290 memsize: 0xce758
  80. Processing 4262 relocs. Offset value of 0x79cfc000
  81.  
  82.  
  83. coreboot-4.10-854-g3d4923d85a-2.0-beta2 Wed Oct 2 11:26:53 UTC 2019 ramstage starting (log level: 7)...
  84. Normal boot.
  85. BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
  86. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  87. CBFS: Locating 'cpu_microcode_blob.bin'
  88. CBFS: Found @ offset 391340 size 61000
  89. microcode: sig=0x406e3 pf=0x80 revision=0xcb
  90. Skip microcode update
  91. CBFS: 'Master Header Locator' located CBFS at [280200:800000)
  92. CBFS: Locating 'fsps.bin'
  93. CBFS: Found @ offset 8edc0 size 2e000
  94. Detected 2 core, 4 thread CPU.
  95. Setting up SMI for CPU
  96. IED base = 0x7b400000
  97. IED size = 0x00400000
  98. Will perform SMM setup.
  99. CPU: Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz.
  100. Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
  101. Processing 16 relocs. Offset value of 0x00030000
  102. Attempting to start 3 APs
  103. Waiting for 10ms after sending INIT.
  104. Waiting for 1st SIPI to complete...AP: slot 3 apic_id 1.
  105. done.
  106. AP: slot 2 apic_id 2.
  107. Waiting for 2nd SIPI to complete...done.
  108. AP: slot 1 apic_id 3.
  109. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
  110. Processing 13 relocs. Offset value of 0x00038000
  111. SMM Module: stub loaded at 00038000. Will call 7ab1f08f(00000000)
  112. Installing SMM handler to 0x7b000000
  113. Loading module at 7b010000 with entry 7b010092. filesize: 0xf48 memsize: 0x4f60
  114. Processing 107 relocs. Offset value of 0x7b010000
  115. Loading module at 7b008000 with entry 7b008000. filesize: 0x1a8 memsize: 0x1a8
  116. Processing 13 relocs. Offset value of 0x7b008000
  117. SMM Module: placing jmp sequence at 7b007c00 rel16 0x03fd
  118. SMM Module: placing jmp sequence at 7b007800 rel16 0x07fd
  119. SMM Module: placing jmp sequence at 7b007400 rel16 0x0bfd
  120. SMM Module: stub loaded at 7b008000. Will call 7b010092(00000000)
  121. Clearing SMI status registers
  122. SMI_STS: PM1
  123. WAK PWRBTN TMROF TCO_STS: SECOND_TO
  124. New SMBASE 0x7b000000
  125. In relocation handler: CPU 0
  126. New SMBASE=0x7b000000 IEDBASE=0x7b400000
  127. Writing SMRR. base = 0x7b000006, mask=0xff800800
  128. Relocation complete.
  129. New SMBASE 0x7afff400
  130. In relocation handler: CPU 3
  131. New SMBASE=0x7afff400 IEDBASE=0x7b400000
  132. Writing SMRR. base = 0x7b000006, mask=0xff800800
  133. Relocation complete.
  134. New SMBASE 0x7afff800
  135. In relocation handler: CPU 2
  136. New SMBASE=0x7afff800 IEDBASE=0x7b400000
  137. Writing SMRR. base = 0x7b000006, mask=0xff800800
  138. Relocation complete.
  139. New SMBASE 0x7afffc00
  140. In relocation handler: CPU 1
  141. New SMBASE=0x7afffc00 IEDBASE=0x7b400000
  142. Writing SMRR. base = 0x7b000006, mask=0xff800800
  143. Relocation complete.
  144. Initializing CPU #0
  145. CPU: vendor Intel device 406e3
  146. CPU: family 06, model 4e, stepping 03
  147. Clearing out pending MCEs
  148. Setting up local APIC...
  149. apic_id: 0x00 done.
  150. cpu: energy policy set to 6
  151. Turbo is available but hidden
  152. Turbo is available and visible
  153. SGX : param.enable = 0
  154. Skip microcode update
  155. CPU #0 initialized
  156. Initializing CPU #3
  157. Initializing CPU #2
  158. Initializing CPU #1
  159. CPU: vendor Intel device 406e3
  160. CPU: family 06, model 4e, stepping 03
  161. CPU: vendor Intel device 406e3
  162. CPU: family 06, model 4e, stepping 03
  163. Clearing out pending MCEs
  164. Clearing out pending MCEs
  165. Setting up local APIC...
  166. CPU: vendor Intel device 406e3
  167. CPU: family 06, model 4e, stepping 03
  168. Clearing out pending MCEs
  169. Setting up local APIC...
  170. Setting up local APIC...
  171. apic_id: 0x02 done.
  172. apic_id: 0x03 done.
  173. cpu: energy policy set to 6
  174. cpu: energy policy set to 6
  175. Skip microcode update
  176. CPU #2 initialized
  177. Skip microcode update
  178. CPU #1 initialized
  179. apic_id: 0x01 done.
  180. cpu: energy policy set to 6
  181. Skip microcode update
  182. CPU #3 initialized
  183. bsp_do_flight_plan done after 17 msecs.
  184. CPU: frequency set to 3100 MHz
  185. Enabling SMIs.
  186. Locking SMM.
  187. VMX status: enabled
  188. SGX: pre-conditions not met
  189. VMX status: enabled
  190. VMX status: enabled
  191. VMX status: enabled
  192. SGX: pre-conditions not met
  193. SGX: pre-conditions not met
  194. SGX: pre-conditions not met
  195. IA32_FEATURE_CONTROL status: locked
  196. IA32_FEATURE_CONTROL status: locked
  197. IA32_FEATURE_CONTROL status: locked
  198. IA32_FEATURE_CONTROL status: locked
  199. ERROR: Unknown MCH in VR-config
  200. ERROR: Unknown MCH in VR-config
  201. ERROR: Unknown MCH in VR-config
  202. ERROR: Unknown MCH in VR-config
  203. ERROR: Unknown MCH in VR-config
  204. ERROR: Unknown MCH in VR-config
  205. ERROR: Unknown MCH in VR-config
  206. ERROR: Unknown MCH in VR-config
  207. ITSS IRQ Polarities Before:
  208. IPC0: 0x00ff4000
  209. IPC1: 0x00000007
  210. IPC2: 0x00000000
  211. IPC3: 0x00000000
  212. ITSS IRQ Polarities After:
  213. IPC0: 0x00ff4000
  214. IPC1: 0x00000007
  215. IPC2: 0x00000000
  216. IPC3: 0x00000000
  217. Override DT after FSP-S, PCH is [BUG] PCIE Root Port id 0xffff is not found
  218. BS: BS_DEV_INIT_CHIPS times (us): entry 111369 run 1050324 exit 0
  219. Enumerating buses...
  220. CPU_CLUSTER: 0 enabled
  221. DOMAIN: 0000 enabled
  222. PCI: pci_scan_bus for bus 00
  223. PCI: 00:00.0 [8086/1904] enabled
  224. PCI: 00:02.0 [8086/1916] enabled
  225. PCI: 00:14.0 [8086/9d2f] enabled
  226. PCI: 00:14.1 [8086/9d30] enabled
  227. PCI: 00:14.2 [8086/9d31] enabled
  228. PCI: Static device PCI: 00:15.0 not found, disabling it.
  229. PCI: Static device PCI: 00:15.1 not found, disabling it.
  230. PCI: 00:16.0 [8086/9d3a] enabled
  231. PCI: 00:17.0 [8086/9d03] enabled
  232. PCI: Static device PCI: 00:1c.0 not found, disabling it.
  233. PCI: 00:1d.0 [8086/9d18] enabled
  234. PCI: 00:1d.1 [8086/9d19] enabled
  235. PCI: 00:1f.0 [8086/9d48] enabled
  236. PCI: 00:1f.2 [8086/9d21] enabled
  237. PCI: 00:1f.3 [8086/9d70] enabled
  238. PCI: 00:1f.4 [8086/9d23] enabled
  239. PCI: 00:1f.5 [8086/9d24] enabled
  240. PCI: Leftover static devices:
  241. PCI: 00:15.0
  242. PCI: 00:15.1
  243. PCI: 00:16.1
  244. PCI: 00:16.2
  245. PCI: 00:16.3
  246. PCI: 00:16.4
  247. PCI: 00:1c.0
  248. PCI: 00:1c.1
  249. PCI: 00:1c.2
  250. PCI: 00:1c.3
  251. PCI: 00:1c.4
  252. PCI: 00:1c.5
  253. PCI: 00:1c.6
  254. PCI: 00:1c.7
  255. PCI: 00:1d.2
  256. PCI: 00:1d.3
  257. PCI: 00:1f.1
  258. PCI: 00:1f.6
  259. PCI: Check your devicetree.cb.
  260. scan_bus: scanning of bus PCI: 00:14.0 took 0 usecs
  261. PCI: pci_scan_bus for bus 01
  262. PCI: 01:00.0 [10ec/8168] enabled
  263. Enabling Common Clock Configuration
  264. ASPM: Enabled L1
  265. scan_bus: scanning of bus PCI: 00:1d.0 took 1234 usecs
  266. PCI: pci_scan_bus for bus 02
  267. PCI: 02:00.0 [168c/003e] enabled
  268. Enabling Common Clock Configuration
  269. ASPM: Enabled L0s and L1
  270. scan_bus: scanning of bus PCI: 00:1d.1 took 1276 usecs
  271. PNP: 0c31.0 enabled
  272. scan_bus: scanning of bus PCI: 00:1f.0 took 139 usecs
  273. scan_bus: scanning of bus PCI: 00:1f.2 took 0 usecs
  274. scan_bus: scanning of bus PCI: 00:1f.3 took 0 usecs
  275. scan_bus: scanning of bus PCI: 00:1f.4 took 0 usecs
  276. scan_bus: scanning of bus PCI: 00:1f.5 took 0 usecs
  277. scan_bus: scanning of bus DOMAIN: 0000 took 13127 usecs
  278. scan_bus: scanning of bus Root Device took 13790 usecs
  279. done
  280. FMAP: area RW_MRC_CACHE found @ 270000 (65536 bytes)
  281. MRC: Checking cached data update for 'RW_MRC_CACHE'.
  282. MRC: no data in 'RW_MRC_CACHE'
  283. MRC: cache data 'RW_MRC_CACHE' needs update.
  284. MRC: Could not find region 'UNIFIED_MRC_CACHE'
  285. FMAP: area RW_MRC_CACHE found @ 270000 (65536 bytes)
  286. MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  287. BS: BS_DEV_ENUMERATE times (us): entry 0 run 14373 exit 14790
  288. found VGA at PCI: 00:02.0
  289. Setting up VGA for PCI: 00:02.0
  290. Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  291. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  292. Allocating resources...
  293. Reading resources...
  294. Done reading resources.
  295. Setting resources...
  296. PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
  297. PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
  298. PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
  299. PCI: 00:14.0 10 <- [0x00d1500000 - 0x00d150ffff] size 0x00010000 gran 0x10 mem64
  300. PCI: 00:14.1 10 <- [0x00d1000000 - 0x00d11fffff] size 0x00200000 gran 0x15 mem64
  301. PCI: 00:14.1 18 <- [0x00d152a000 - 0x00d152afff] size 0x00001000 gran 0x0c mem64
  302. PCI: 00:14.2 10 <- [0x00d152b000 - 0x00d152bfff] size 0x00001000 gran 0x0c mem64
  303. PCI: 00:16.0 10 <- [0x00d152c000 - 0x00d152cfff] size 0x00001000 gran 0x0c mem64
  304. PCI: 00:17.0 10 <- [0x00d1528000 - 0x00d1529fff] size 0x00002000 gran 0x0d mem
  305. PCI: 00:17.0 14 <- [0x00d152f000 - 0x00d152f0ff] size 0x00000100 gran 0x08 mem
  306. PCI: 00:17.0 18 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io
  307. PCI: 00:17.0 1c <- [0x0000003068 - 0x000000306b] size 0x00000004 gran 0x02 io
  308. PCI: 00:17.0 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
  309. PCI: 00:17.0 24 <- [0x00d152e000 - 0x00d152e7ff] size 0x00000800 gran 0x0b mem
  310. PCI: 00:1d.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io
  311. PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  312. PCI: 00:1d.0 20 <- [0x00d1400000 - 0x00d14fffff] size 0x00100000 gran 0x14 bus 01 mem
  313. PCI: 01:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
  314. PCI: 01:00.0 18 <- [0x00d1404000 - 0x00d1404fff] size 0x00001000 gran 0x0c mem64
  315. PCI: 01:00.0 20 <- [0x00d1400000 - 0x00d1403fff] size 0x00004000 gran 0x0e mem64
  316. PCI: 00:1d.1 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 02 io
  317. PCI: 00:1d.1 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
  318. PCI: 00:1d.1 20 <- [0x00d1200000 - 0x00d13fffff] size 0x00200000 gran 0x14 bus 02 mem
  319. PCI: 02:00.0 10 <- [0x00d1200000 - 0x00d13fffff] size 0x00200000 gran 0x15 mem64
  320. PCI: 00:1f.2 10 <- [0x00d1520000 - 0x00d1523fff] size 0x00004000 gran 0x0e mem
  321. PCI: 00:1f.3 10 <- [0x00d1524000 - 0x00d1527fff] size 0x00004000 gran 0x0e mem64
  322. PCI: 00:1f.3 20 <- [0x00d1510000 - 0x00d151ffff] size 0x00010000 gran 0x10 mem64
  323. PCI: 00:1f.4 10 <- [0x00d1530000 - 0x00d15300ff] size 0x00000100 gran 0x08 mem64
  324. PCI: 00:1f.5 10 <- [0x00d152d000 - 0x00d152dfff] size 0x00001000 gran 0x0c mem
  325. Done setting resources.
  326. Done allocating resources.
  327. BS: BS_DEV_RESOURCES times (us): entry 0 run 19014 exit 29
  328. Enabling resources...
  329. PCI: 00:00.0 subsystem <- 8086/1904
  330. PCI: 00:00.0 cmd <- 06
  331. PCI: 00:02.0 subsystem <- 8086/1916
  332. PCI: 00:02.0 cmd <- 03
  333. PCI: 00:14.0 subsystem <- 8086/9d2f
  334. PCI: 00:14.0 cmd <- 02
  335. PCI: 00:14.1 subsystem <- 8086/9d30
  336. PCI: 00:14.1 cmd <- 02
  337. PCI: 00:14.2 subsystem <- 8086/9d31
  338. PCI: 00:14.2 cmd <- 02
  339. PCI: 00:16.0 subsystem <- 8086/9d3a
  340. PCI: 00:16.0 cmd <- 02
  341. PCI: 00:17.0 subsystem <- 8086/9d03
  342. PCI: 00:17.0 cmd <- 03
  343. PCI: 00:1d.0 bridge ctrl <- 0003
  344. PCI: 00:1d.0 subsystem <- 8086/9d18
  345. PCI: 00:1d.0 cmd <- 07
  346. PCI: 00:1d.1 bridge ctrl <- 0003
  347. PCI: 00:1d.1 subsystem <- 8086/9d19
  348. PCI: 00:1d.1 cmd <- 06
  349. PCI: 00:1f.0 subsystem <- 8086/9d48
  350. PCI: 00:1f.0 cmd <- 07
  351. PCI: 00:1f.2 subsystem <- 8086/9d21
  352. PCI: 00:1f.2 cmd <- 02
  353. PCI: 00:1f.3 subsystem <- 8086/9d70
  354. PCI: 00:1f.3 cmd <- 02
  355. PCI: 00:1f.4 subsystem <- 8086/9d23
  356. PCI: 00:1f.4 cmd <- 03
  357. PCI: 00:1f.5 subsystem <- 8086/9d24
  358. PCI: 00:1f.5 cmd <- 406
  359. PCI: 01:00.0 cmd <- 03
  360. PCI: 02:00.0 cmd <- 02
  361. done.
  362. ME: Version : 11.8.50.3399
  363. BS: BS_DEV_ENABLE times (us): entry 9007 run 6872 exit 1560241
  364. tis_probe: No TPM device found
  365. tlcl_lib_init: tis_init returned error
  366. TPM: Can't initialize.
  367. Initializing devices...
  368. Root Device init ...
  369. Root Device init finished in 144 usecs
  370. CPU_CLUSTER: 0 init ...
  371. CPU_CLUSTER: 0 init finished in 176 usecs
  372. PCI: 00:00.0 init ...
  373. CPU TDP: 15 Watts
  374. CPU PL2 = 35 Watts
  375. PCI: 00:00.0 init finished in 1450 usecs
  376. PCI: 00:02.0 init ...
  377. [2.793314] HW.GFX.GMA.Initialize
  378. [2.793539] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  379. [2.793878] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
  380. [2.794404] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  381. [2.794920] HW.GFX.GMA.Registers.Read: 0x0004af01 <- 0x000c7210:PCH_PP_DIVISOR
  382. [2.795505] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS
  383. [2.795931] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
  384. [2.796507] HW.GFX.GMA.Registers.Write: 0x08340001 -> 0x000c7208:PCH_PP_ON_DELAYS
  385. [2.797016] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS
  386. [2.825187] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  387. [2.825846] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS
  388. [2.826517] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR
  389. [2.826997] HW.GFX.GMA.Registers.Read: 0x0004af01 <- 0x000c7210:PCH_PP_DIVISOR
  390. [2.827485] HW.GFX.GMA.Registers.Write: 0x0004af07 -> 0x000c7210:PCH_PP_DIVISOR
  391. [2.827976] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
  392. [2.828420] HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7204:PCH_PP_CONTROL
  393. [2.828992] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x000c7204:PCH_PP_CONTROL
  394. [2.829506] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  395. [2.829864] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  396. [2.830450] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  397. [2.830868] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL
  398. [2.831391] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL
  399. [2.831929] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  400. [2.832317] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  401. [2.832803] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  402. [2.833211] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL
  403. [2.833683] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL
  404. [2.834226] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  405. [2.834615] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  406. [2.835111] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  407. [2.835546] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL
  408. [2.836054] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL
  409. [2.836596] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
  410. [2.837168] HW.GFX.GMA.Registers.Write: 0x000000a2 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
  411. [2.837695] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
  412. [2.838201] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
  413. [2.838783] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
  414. [2.839379] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
  415. [2.839967] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
  416. [2.840554] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
  417. [2.841146] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
  418. [2.841739] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
  419. [2.842327] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
  420. [2.842926] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
  421. [2.843508] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
  422. [2.844102] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
  423. [2.844702] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
  424. [2.845289] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
  425. [2.845795] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
  426. [2.846395] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
  427. [2.846984] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
  428. [2.847576] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
  429. [2.848165] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
  430. [2.848757] HW.GFX.GMA.Registers.Write: 0x000000a2 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
  431. [2.849345] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
  432. [2.849935] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
  433. [2.850516] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
  434. [2.851107] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
  435. [2.851708] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
  436. [2.852290] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
  437. [2.852859] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
  438. [2.853447] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
  439. [2.854025] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
  440. [2.854616] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
  441. [2.855207] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
  442. [2.855796] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
  443. [2.856376] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
  444. [2.856962] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
  445. [2.857527] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
  446. [2.858114] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
  447. [2.858705] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
  448. [2.859278] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
  449. [2.859855] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
  450. [2.860448] HW.GFX.GMA.Registers.Write: 0x000000a2 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
  451. [2.861038] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
  452. [2.861551] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
  453. [2.862144] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
  454. [2.862735] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
  455. [2.863322] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
  456. [2.863921] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
  457. [2.864490] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
  458. [2.865010] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
  459. [2.865529] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
  460. [2.866098] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
  461. [2.866680] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
  462. [2.867271] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
  463. [2.867857] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
  464. [2.868441] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
  465. [2.869021] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
  466. [2.869622] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
  467. [2.870213] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
  468. [2.870804] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
  469. [2.871385] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
  470. [2.871884] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  471. [2.872472] HW.GFX.GMA.Registers.Write: 0x00124900 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  472. [2.873124] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
  473. [2.873536] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
  474. [2.874069] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
  475. [2.874609] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2
  476. [2.875077] HW.GFX.GMA.Registers.Read: 0x00a00000 <- 0x0006c05c:DPLL_CTRL2
  477. [2.875602] HW.GFX.GMA.Registers.Write: 0x00af8000 -> 0x0006c05c:DPLL_CTRL2
  478. [2.876130] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
  479. [2.876627] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
  480. [2.877177] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
  481. [2.877724] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
  482. [2.878340] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  483. [2.878695] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  484. [2.879263] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  485. [2.879841] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  486. [2.880334] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  487. [2.880836] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  488. [2.881390] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  489. [2.881932] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
  490. [2.882452] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  491. [2.883035] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
  492. [2.883625] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  493. [2.884294] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
  494. [2.884931] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  495. [2.885287] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  496. [2.885858] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  497. [2.886445] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  498. [2.887013] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  499. [2.887515] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  500. [2.888054] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  501. [2.888598] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
  502. [2.889125] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  503. [2.889706] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  504. [2.890281] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
  505. [2.890951] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
  506. [2.891472] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
  507. [2.891940] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
  508. [2.892466] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
  509. [2.892991] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
  510. [2.893608] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
  511. [2.894007] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  512. [2.894622] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  513. [2.895177] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  514. [2.895743] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  515. [2.896264] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  516. [2.896880] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
  517. [2.897436] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
  518. [2.897813] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  519. [2.898363] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  520. [2.898871] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  521. [2.899381] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  522. [2.899908] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  523. [2.900524] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
  524. [2.901094] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
  525. [2.901518] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  526. [2.902133] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  527. [2.902690] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  528. [2.903262] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  529. [2.903781] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  530. [2.904339] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
  531. [2.904737] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL
  532. [2.905240] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL
  533. [2.905753] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
  534. [2.906363] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
  535. [2.906837] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ
  536. [2.907395] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ
  537. [2.907955] HW.GFX.GMA.Panel.On
  538. [2.908172] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  539. [2.908585] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  540. [2.909139] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  541. [2.909641] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  542. [2.910193] HW.GFX.GMA.Registers.Write: 0x0000000b -> 0x000c7204:PCH_PP_CONTROL
  543. [2.910748] HW.GFX.GMA.Panel.Wait_On
  544. [3.120749] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  545. [3.121400] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  546. [3.121913] HW.GFX.GMA.Registers.Read: 0x0000000b <- 0x000c7204:PCH_PP_CONTROL
  547. [3.122467] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  548. [3.123023] HW.GFX.GMA.Display_Probing.Read_EDID
  549. [3.123350] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  550. [3.123706] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  551. [3.124256] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  552. [3.124833] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  553. [3.125386] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  554. [3.125961] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  555. [3.126503] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  556. [3.127024] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  557. [3.127697] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  558. [3.128211] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  559. [3.128774] HW.GFX.GMA.Registers.Write: 0x7000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  560. [3.129289] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  561. [3.129933] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  562. [3.130288] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  563. [3.130836] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  564. [3.131367] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  565. [3.131820] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  566. [3.132369] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  567. [3.132907] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  568. [3.133475] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  569. [3.134019] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  570. [3.134582] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  571. [3.134954] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  572. [3.135448] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  573. [3.135955] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  574. [3.136522] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  575. [3.136938] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  576. [3.137421] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  577. [3.137902] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  578. [3.138529] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  579. [3.139037] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  580. [3.139543] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  581. [3.139904] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  582. [3.140416] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064014:DDI_AUX_DATA_A_1
  583. [3.140963] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  584. [3.141397] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  585. [3.141899] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  586. [3.142471] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  587. [3.143099] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  588. [3.143580] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  589. [3.144140] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  590. [3.144521] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  591. [3.145063] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064014:DDI_AUX_DATA_A_1
  592. [3.145631] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  593. [3.146082] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  594. [3.146631] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  595. [3.147180] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  596. [3.147810] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  597. [3.148355] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  598. [3.148929] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  599. [3.149292] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  600. [3.149788] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  601. [3.150352] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  602. [3.150806] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  603. [3.151352] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  604. [3.151892] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  605. [3.152526] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  606. [3.152998] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  607. [3.154059] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  608. [3.154461] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  609. [3.155007] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  610. [3.155580] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  611. [3.156028] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  612. [3.156576] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  613. [3.157118] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  614. [3.157758] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  615. [3.158301] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064014:DDI_AUX_DATA_A_1
  616. [3.158868] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064018:DDI_AUX_DATA_A_2
  617. [3.159429] HW.GFX.GMA.Registers.Read: 0x0030e46f <- 0x0006401c:DDI_AUX_DATA_A_3
  618. [3.159925] HW.GFX.GMA.Registers.Read: 0x04000000 <- 0x00064020:DDI_AUX_DATA_A_4
  619. [3.160490] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  620. [3.161059] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  621. [3.161465] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  622. [3.162009] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  623. [3.162576] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  624. [3.163027] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  625. [3.163573] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  626. [3.164112] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  627. [3.164758] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  628. [3.165299] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  629. [3.166363] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  630. [3.166759] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  631. [3.167300] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  632. [3.167868] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  633. [3.168317] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  634. [3.168872] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  635. [3.169406] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  636. [3.170024] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  637. [3.170567] HW.GFX.GMA.Registers.Read: 0x00001801 <- 0x00064014:DDI_AUX_DATA_A_1
  638. [3.171132] HW.GFX.GMA.Registers.Read: 0x04952313 <- 0x00064018:DDI_AUX_DATA_A_2
  639. [3.171692] HW.GFX.GMA.Registers.Read: 0x78eadc95 <- 0x0006401c:DDI_AUX_DATA_A_3
  640. [3.172250] HW.GFX.GMA.Registers.Read: 0xa35855a0 <- 0x00064020:DDI_AUX_DATA_A_4
  641. [3.172805] HW.GFX.GMA.Registers.Read: 0x26000000 <- 0x00064024:DDI_AUX_DATA_A_5
  642. [3.173373] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  643. [3.173770] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  644. [3.174285] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  645. [3.174810] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  646. [3.175234] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  647. [3.175776] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  648. [3.176269] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  649. [3.176854] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  650. [3.177343] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  651. [3.178418] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  652. [3.178780] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  653. [3.179289] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  654. [3.179799] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  655. [3.180247] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  656. [3.180809] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  657. [3.181300] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  658. [3.181851] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  659. [3.182423] HW.GFX.GMA.Registers.Read: 0x000d5054 <- 0x00064014:DDI_AUX_DATA_A_1
  660. [3.182931] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00064018:DDI_AUX_DATA_A_2
  661. [3.183508] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x0006401c:DDI_AUX_DATA_A_3
  662. [3.184026] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x00064020:DDI_AUX_DATA_A_4
  663. [3.184594] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064024:DDI_AUX_DATA_A_5
  664. [3.185116] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  665. [3.185476] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  666. [3.185973] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  667. [3.186480] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  668. [3.186887] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  669. [3.187375] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  670. [3.187955] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  671. [3.188533] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  672. [3.189010] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  673. [3.190100] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  674. [3.190501] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  675. [3.190974] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  676. [3.191465] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  677. [3.191905] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  678. [3.192452] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  679. [3.192994] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  680. [3.193637] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  681. [3.194179] HW.GFX.GMA.Registers.Read: 0x00010101 <- 0x00064014:DDI_AUX_DATA_A_1
  682. [3.194747] HW.GFX.GMA.Registers.Read: 0x0101012e <- 0x00064018:DDI_AUX_DATA_A_2
  683. [3.195310] HW.GFX.GMA.Registers.Read: 0x3680a070 <- 0x0006401c:DDI_AUX_DATA_A_3
  684. [3.195884] HW.GFX.GMA.Registers.Read: 0x381f4030 <- 0x00064020:DDI_AUX_DATA_A_4
  685. [3.196447] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064024:DDI_AUX_DATA_A_5
  686. [3.197012] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  687. [3.197420] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  688. [3.197964] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  689. [3.198454] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  690. [3.198848] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  691. [3.199389] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  692. [3.199929] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  693. [3.200564] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  694. [3.201113] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  695. [3.202183] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  696. [3.202582] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  697. [3.203127] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  698. [3.203694] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  699. [3.204146] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  700. [3.204704] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  701. [3.205248] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  702. [3.205807] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  703. [3.206275] HW.GFX.GMA.Registers.Read: 0x00350059 <- 0x00064014:DDI_AUX_DATA_A_1
  704. [3.206848] HW.GFX.GMA.Registers.Read: 0xc2100000 <- 0x00064018:DDI_AUX_DATA_A_2
  705. [3.207414] HW.GFX.GMA.Registers.Read: 0x1a000000 <- 0x0006401c:DDI_AUX_DATA_A_3
  706. [3.207979] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  707. [3.208544] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  708. [3.209112] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  709. [3.209511] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  710. [3.210056] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  711. [3.210622] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  712. [3.211076] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  713. [3.211624] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  714. [3.212159] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  715. [3.212796] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  716. [3.213267] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  717. [3.214256] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  718. [3.214653] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  719. [3.215196] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  720. [3.215761] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  721. [3.216212] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  722. [3.216763] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  723. [3.217305] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  724. [3.217944] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  725. [3.218487] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  726. [3.219054] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2
  727. [3.219627] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006401c:DDI_AUX_DATA_A_3
  728. [3.220178] HW.GFX.GMA.Registers.Read: 0x0000fe00 <- 0x00064020:DDI_AUX_DATA_A_4
  729. [3.220668] HW.GFX.GMA.Registers.Read: 0x4c000000 <- 0x00064024:DDI_AUX_DATA_A_5
  730. [3.221233] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  731. [3.221635] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  732. [3.222180] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  733. [3.222757] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  734. [3.223209] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  735. [3.223754] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  736. [3.224293] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  737. [3.224936] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  738. [3.225481] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  739. [3.226541] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  740. [3.226946] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  741. [3.227414] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  742. [3.227980] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  743. [3.228428] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  744. [3.228976] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  745. [3.229520] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  746. [3.230144] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  747. [3.230697] HW.GFX.GMA.Registers.Read: 0x00472044 <- 0x00064014:DDI_AUX_DATA_A_1
  748. [3.231267] HW.GFX.GMA.Registers.Read: 0x6973706c <- 0x00064018:DDI_AUX_DATA_A_2
  749. [3.231828] HW.GFX.GMA.Registers.Read: 0x61790a20 <- 0x0006401c:DDI_AUX_DATA_A_3
  750. [3.232389] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064020:DDI_AUX_DATA_A_4
  751. [3.232955] HW.GFX.GMA.Registers.Read: 0xfe000000 <- 0x00064024:DDI_AUX_DATA_A_5
  752. [3.233516] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  753. [3.233913] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  754. [3.234456] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  755. [3.235005] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  756. [3.235447] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  757. [3.235987] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  758. [3.236514] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  759. [3.237085] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  760. [3.237595] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064014:DDI_AUX_DATA_A_1
  761. [3.238653] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  762. [3.239010] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  763. [3.239507] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  764. [3.240060] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  765. [3.240472] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  766. [3.240979] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  767. [3.241531] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  768. [3.242106] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  769. [3.242605] HW.GFX.GMA.Registers.Read: 0x00004c50 <- 0x00064014:DDI_AUX_DATA_A_1
  770. [3.243134] HW.GFX.GMA.Registers.Read: 0x31353657 <- 0x00064018:DDI_AUX_DATA_A_2
  771. [3.243638] HW.GFX.GMA.Registers.Read: 0x46362d53 <- 0x0006401c:DDI_AUX_DATA_A_3
  772. [3.244181] HW.GFX.GMA.Registers.Read: 0x50423100 <- 0x00064020:DDI_AUX_DATA_A_4
  773. [3.244720] HW.GFX.GMA.Registers.Read: 0x7b000000 <- 0x00064024:DDI_AUX_DATA_A_5
  774. [3.245225] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  775. [3.245579] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  776. [3.246120] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064014:DDI_AUX_DATA_A_1
  777. [3.246637] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  778. [3.247089] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  779. [3.247612] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  780. [3.248091] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  781. [3.248728] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  782. [3.249272] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  783. [3.249792] EDID+0x0000: 00 ff ff ff ff ff ff 00 30 e4 6f 04 00 00 00 00
  784. [3.250280] EDID+0x0010: 00 18 01 04 95 23 13 78 ea dc 95 a3 58 55 a0 26
  785. [3.250773] EDID+0x0020: 0d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
  786. [3.251310] EDID+0x0030: 01 01 01 01 01 01 2e 36 80 a0 70 38 1f 40 30 20
  787. [3.251843] EDID+0x0040: 35 00 59 c2 10 00 00 1a 00 00 00 00 00 00 00 00
  788. [3.252307] EDID+0x0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4c
  789. [3.252789] EDID+0x0060: 47 20 44 69 73 70 6c 61 79 0a 20 20 00 00 00 fe
  790. [3.253277] EDID+0x0070: 00 4c 50 31 35 36 57 46 36 2d 53 50 42 31 00 7b
  791. [3.253815] HW.GFX.GMA.Display_Probing.Read_EDID
  792. [3.254139] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  793. [3.254495] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  794. [3.255062] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  795. [3.255564] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  796. [3.256118] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  797. [3.256691] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  798. [3.257233] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  799. [3.257772] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
  800. [3.258293] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  801. [3.258874] HW.GFX.GMA.Registers.Write: 0xf000000f -> 0x00045404:PWR_WELL_CTL_DRIVER
  802. [3.259454] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  803. [3.260122] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
  804. [3.260749] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  805. [3.261105] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  806. [3.261684] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  807. [3.262268] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  808. [3.262767] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  809. [3.263278] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  810. [3.263817] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  811. [3.264360] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  812. [3.265041] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
  813. [3.265569] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  814. [3.266148] HW.GFX.GMA.Registers.Write: 0xf000002f -> 0x00045404:PWR_WELL_CTL_DRIVER
  815. [3.266731] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  816. [3.267407] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  817. [3.267804] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  818. [3.268348] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  819. [3.268916] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  820. [3.269366] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  821. [3.269857] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  822. [3.270395] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  823. [3.271039] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  824. [3.271584] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  825. [3.271976] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  826. [3.272524] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  827. [3.273063] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  828. [3.273514] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  829. [3.274041] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  830. [3.274560] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  831. [3.275205] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  832. [3.275732] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  833. [3.276118] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  834. [3.276583] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  835. [3.277140] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  836. [3.277590] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  837. [3.278122] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  838. [3.278659] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  839. [3.279305] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  840. [3.279847] HW.GFX.GMA.Display_Probing.Read_EDID
  841. [3.280172] HW.GFX.GMA.I2C.I2C_Read
  842. [3.280423] HW.GFX.GMA.I2C.Init_GMBUS
  843. [3.280648] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  844. [3.281113] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  845. [3.281685] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  846. [3.282260] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  847. [3.282891] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
  848. [3.283424] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
  849. [3.283953] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  850. [3.284479] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  851. [3.285006] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  852. [3.285540] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  853. [3.286176] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  854. [3.286701] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
  855. [3.287321] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  856. [3.287848] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  857. [3.288316] HW.GFX.GMA.I2C.Release_GMBUS
  858. [3.288555] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  859. [3.289087] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  860. [3.289630] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  861. [3.290162] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  862. [3.290735] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  863. [3.291310] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
  864. [3.291686] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  865. [3.292256] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  866. [3.292840] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  867. [3.293400] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  868. [3.293976] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  869. [3.294521] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  870. [3.294992] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
  871. [3.295308] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  872. [3.295869] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  873. [3.296450] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  874. [3.297019] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  875. [3.297586] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  876. [3.298130] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  877. [3.298675] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
  878. [3.299038] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  879. [3.299606] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  880. [3.300201] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  881. [3.300772] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  882. [3.301347] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  883. [3.301829] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  884. [3.302310] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  885. [3.302982] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
  886. [3.303524] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  887. [3.304114] HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
  888. [3.304701] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
  889. [3.305064] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  890. [3.305630] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  891. [3.306215] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  892. [3.306787] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  893. [3.307364] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  894. [3.307907] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  895. [3.308453] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  896. [3.309044] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
  897. [3.309511] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  898. [3.310097] HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
  899. [3.310678] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
  900. [3.311042] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  901. [3.311609] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  902. [3.312197] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  903. [3.312774] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  904. [3.313349] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  905. [3.313891] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  906. [3.314432] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  907. [3.315104] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS
  908. [3.315615] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  909. [3.316103] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS
  910. [3.316671] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
  911. [3.317211] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  912. [3.317792] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  913.  
  914. [3.318402] CONFIG =>
  915. [3.318559] (Primary =>
  916. [3.318754] (Port => Internal,
  917. [3.319000] Framebuffer =>
  918. [3.319232] (Width => 1920,
  919. [3.319526] Height => 1080,
  920. [3.319807] Start_X => 0,
  921. [3.320068] Start_Y => 0,
  922. [3.320330] Stride => 1920,
  923. [3.320614] V_Stride => 1080,
  924. [3.320897] Tiling => Linear ,
  925. [3.321198] Rotation => No_Rotation,
  926. [3.321529] Offset => 0x00000000,
  927. [3.321831] BPC => 8),
  928. [3.322083] Mode =>
  929. [3.322272] (Dotclock => 138700000,
  930. [3.322598] H_Visible => 1920,
  931. [3.322890] H_Sync_Begin => 1968,
  932. [3.323191] H_Sync_End => 2000,
  933. [3.323534] H_Total => 2080,
  934. [3.323881] V_Visible => 1080,
  935. [3.324227] V_Sync_Begin => 1083,
  936. [3.324566] V_Sync_End => 1088,
  937. [3.324918] V_Total => 1111,
  938. [3.325267] H_Sync_Active_High => True,
  939. [3.325598] V_Sync_Active_High => False,
  940. [3.325936] BPC => 6)),
  941. [3.326282] Secondary =>
  942. [3.326476] (Port => Disabled,
  943. [3.326732] Framebuffer =>
  944. [3.326961] (Width => 1,
  945. [3.327226] Height => 1,
  946. [3.327491] Start_X => 0,
  947. [3.327755] Start_Y => 0,
  948. [3.328018] Stride => 1,
  949. [3.328286] V_Stride => 1,
  950. [3.328560] Tiling => Linear ,
  951. [3.328860] Rotation => No_Rotation,
  952. [3.329183] Offset => 0x00000000,
  953. [3.329485] BPC => 8),
  954. [3.329698] Mode =>
  955. [3.329858] (Dotclock => 19200000,
  956. [3.330176] H_Visible => 1,
  957. [3.330510] H_Sync_Begin => 1,
  958. [3.330825] H_Sync_End => 1,
  959. [3.331154] H_Total => 1,
  960. [3.331484] V_Visible => 1,
  961. [3.331811] V_Sync_Begin => 1,
  962. [3.332143] V_Sync_End => 1,
  963. [3.332469] V_Total => 1,
  964. [3.332796] H_Sync_Active_High => False,
  965. [3.333137] V_Sync_Active_High => False,
  966. [3.333475] BPC => 5)),
  967. [3.333820] Tertiary =>
  968. [3.334027] (Port => Disabled,
  969. [3.334274] Framebuffer =>
  970. [3.334502] (Width => 1,
  971. [3.334766] Height => 1,
  972. [3.335031] Start_X => 0,
  973. [3.335295] Start_Y => 0,
  974. [3.335558] Stride => 1,
  975. [3.335835] V_Stride => 1,
  976. [3.336096] Tiling => Linear ,
  977. [3.336395] Rotation => No_Rotation,
  978. [3.336709] Offset => 0x00000000,
  979. [3.336968] BPC => 8),
  980. [3.337181] Mode =>
  981. [3.337339] (Dotclock => 19200000,
  982. [3.337724] H_Visible => 1,
  983. [3.338051] H_Sync_Begin => 1,
  984. [3.338372] H_Sync_End => 1,
  985. [3.338697] H_Total => 1,
  986. [3.339021] V_Visible => 1,
  987. [3.339350] V_Sync_Begin => 1,
  988. [3.339678] V_Sync_End => 1,
  989. [3.340003] V_Total => 1,
  990. [3.340334] H_Sync_Active_High => False,
  991. [3.340676] V_Sync_Active_High => False,
  992. [3.341015] BPC => 5)));
  993. [3.489251] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
  994. [3.489606] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  995. [3.490100] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  996. [3.490682] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  997. [3.491258] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  998. [3.491836] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  999. [3.492379] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1000. [3.492918] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1001. [3.493588] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  1002. [3.494117] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1003. [3.494698] HW.GFX.GMA.Registers.Write: 0x3000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  1004. [3.495284] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1005.  
  1006. [3.495983] Trying to enable port Internal
  1007. [3.496284] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
  1008. [3.496686] HW.GFX.GMA.Panel.On
  1009. [3.496903] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  1010. [3.497313] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1011. [3.497795] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  1012. [3.498226] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1013. [3.498771] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1014. [3.499327] HW.GFX.GMA.Panel.Wait_On
  1015. [3.499575] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  1016. [3.500212] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  1017. [3.500726] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1018. [3.501281] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1019. [3.501846] HW.GFX.GMA.DP_Info.Read_Caps
  1020. [3.502123] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1021. [3.502522] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1022. [3.503068] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064014:DDI_AUX_DATA_A_1
  1023. [3.503644] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1024. [3.504098] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1025. [3.504637] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1026. [3.505178] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1027. [3.505759] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1028. [3.506226] HW.GFX.GMA.Registers.Read: 0x00120ac2 <- 0x00064014:DDI_AUX_DATA_A_1
  1029. [3.506785] HW.GFX.GMA.Registers.Read: 0x41000001 <- 0x00064018:DDI_AUX_DATA_A_2
  1030. [3.507351] HW.GFX.GMA.Registers.Read: 0xc0020000 <- 0x0006401c:DDI_AUX_DATA_A_3
  1031. [3.507918] HW.GFX.GMA.Registers.Read: 0x001f0b00 <- 0x00064020:DDI_AUX_DATA_A_4
  1032.  
  1033. [3.508509] DPCD:
  1034. [3.508640] Rev : 0x12
  1035. [3.508910] Max_Link_Rate : 0x0a
  1036. [3.509169] Max_Lane_Count : 0x02
  1037. [3.509423] TPS3_Supported : 0x40
  1038. [3.509680] Enhanced_Framing: 0x80
  1039. [3.509936] No_Aux_Handshake: 0x40
  1040. [3.510186] Aux_RD_Interval : 0x00
  1041.  
  1042. [3.510477] Trying DP settings: Symbol Rate = 270000000; Lane Count = 2
  1043.  
  1044. [3.510997] HW.GFX.GMA.PLLs.Alloc
  1045. [3.511230] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1
  1046. [3.511758] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1
  1047. [3.512189] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1
  1048. [3.512718] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x0006c058:DPLL_CTRL1
  1049. [3.513243] HW.GFX.GMA.Registers.Read: 0x000000c0 <- 0x0006c058:DPLL_CTRL1
  1050. [3.513710] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL
  1051. [3.514161] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS
  1052. [3.514790] HW.GFX.GMA.Connectors.Pre_On
  1053. [3.515061] HW.GFX.GMA.Connectors.DDI.Pre_On
  1054. [3.515359] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1055. [3.515791] HW.GFX.GMA.Registers.Read: 0x00af8000 <- 0x0006c05c:DPLL_CTRL2
  1056. [3.516315] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2
  1057. [3.516835] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1058. [3.517250] HW.GFX.GMA.Registers.Write: 0x80040080 -> 0x00064040:DP_TP_CTL_A
  1059. [3.517789] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1060. [3.518188] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1061. [3.518736] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1062. [3.519184] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1063. [3.519737] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1064. [3.520279] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1065. [3.521429] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1066. [3.521858] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1067. [3.522208] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1068. [3.522678] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1069. [3.523238] HW.GFX.GMA.Registers.Write: 0x0a820000 -> 0x00064018:DDI_AUX_DATA_A_2
  1070. [3.523801] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1071. [3.524255] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1072. [3.524800] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1073. [3.525350] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1074. [3.525985] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1075. [3.526530] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1076. [3.527092] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1077. [3.527479] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1078. [3.528023] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1079. [3.528590] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1080. [3.529151] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1081. [3.529598] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1082. [3.530142] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1083. [3.530626] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1084. [3.531254] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1085. [3.531799] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1086. [3.532371] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1087. [3.532903] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1088. [3.533301] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1089. [3.533844] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1090. [3.534413] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1091. [3.534979] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1092. [3.535424] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1093. [3.535979] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1094. [3.536521] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1095. [3.537155] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1096. [3.537699] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1097. [3.538366] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1098. [3.538807] HW.GFX.GMA.DP_Info.Read_Link_Status
  1099. [3.539098] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1100. [3.539442] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1101. [3.539985] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1102. [3.540548] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1103. [3.540994] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1104. [3.541542] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1105. [3.542085] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1106. [3.542716] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1107. [3.543254] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1108. [3.543820] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1109.  
  1110. [3.544412] Link Status:
  1111. [3.544585] Lane0:
  1112. [3.544732] CR_Done : 0
  1113. [3.544983] Channel_EQ_Done: 0
  1114. [3.545223] Symbol_Locked : 0
  1115. [3.545463] Lane1:
  1116. [3.545611] CR_Done : 0
  1117. [3.545851] Channel_EQ_Done: 0
  1118. [3.546091] Symbol_Locked : 0
  1119. [3.546343] Interlane_Align_Done: 0
  1120. [3.546566] Adjust0:
  1121. [3.546705] Voltage_Swing: 1
  1122. [3.546901] Pre_Emph : 0
  1123. [3.547101] Adjust1:
  1124. [3.547261] Voltage_Swing: 1
  1125. [3.547486] Pre_Emph : 0
  1126.  
  1127. [3.547742] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1128. [3.548148] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1129. [3.548697] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1130. [3.549150] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1131. [3.549697] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1132. [3.550239] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1133. [3.550783] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1134. [3.551302] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1135. [3.551712] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1136. [3.552255] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1137. [3.552818] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1138. [3.553385] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1139. [3.553837] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1140. [3.554307] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1141. [3.554774] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1142. [3.555411] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1143. [3.555957] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1144. [3.556613] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1145. [3.557110] HW.GFX.GMA.DP_Info.Read_Link_Status
  1146. [3.557433] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1147. [3.557829] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1148. [3.558377] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1149. [3.558947] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1150. [3.559402] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1151. [3.559948] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1152. [3.560489] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1153. [3.561118] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1154. [3.561665] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1155. [3.562228] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1156.  
  1157. [3.562818] Link Status:
  1158. [3.562993] Lane0:
  1159. [3.563140] CR_Done : 0
  1160. [3.563389] Channel_EQ_Done: 0
  1161. [3.563629] Symbol_Locked : 0
  1162. [3.563883] Lane1:
  1163. [3.564030] CR_Done : 0
  1164. [3.564279] Channel_EQ_Done: 0
  1165. [3.564520] Symbol_Locked : 0
  1166. [3.564764] Interlane_Align_Done: 0
  1167. [3.565022] Adjust0:
  1168. [3.565183] Voltage_Swing: 2
  1169. [3.565408] Pre_Emph : 0
  1170. [3.565631] Adjust1:
  1171. [3.565783] Voltage_Swing: 2
  1172. [3.565977] Pre_Emph : 0
  1173.  
  1174. [3.566198] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1175. [3.566592] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1176. [3.567136] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1177. [3.567586] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1178. [3.568133] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1179. [3.568674] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1180. [3.569229] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1181. [3.569732] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1182. [3.570128] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1183. [3.570674] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1184. [3.571237] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1185. [3.571798] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1186. [3.572253] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1187. [3.572808] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1188. [3.573353] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1189. [3.573900] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1190. [3.574453] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1191. [3.575117] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1192. [3.575620] HW.GFX.GMA.DP_Info.Read_Link_Status
  1193. [3.575938] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1194. [3.576342] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1195. [3.576883] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1196. [3.577449] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1197. [3.577899] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1198. [3.578444] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1199. [3.578987] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1200. [3.579618] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1201. [3.580161] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1202. [3.580730] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1203.  
  1204. [3.581297] Link Status:
  1205. [3.581447] Lane0:
  1206. [3.581576] CR_Done : 0
  1207. [3.581796] Channel_EQ_Done: 0
  1208. [3.582001] Symbol_Locked : 0
  1209. [3.582245] Lane1:
  1210. [3.582392] CR_Done : 0
  1211. [3.582642] Channel_EQ_Done: 0
  1212. [3.582881] Symbol_Locked : 0
  1213. [3.583122] Interlane_Align_Done: 0
  1214. [3.583391] Adjust0:
  1215. [3.583553] Voltage_Swing: 2
  1216. [3.583776] Pre_Emph : 0
  1217. [3.584008] Adjust1:
  1218. [3.584171] Voltage_Swing: 2
  1219. [3.584401] Pre_Emph : 0
  1220.  
  1221. [3.584661] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1222. [3.585057] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1223. [3.585597] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1224. [3.586052] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1225. [3.586598] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1226. [3.587141] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1227. [3.587683] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1228. [3.588198] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1229. [3.588597] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1230. [3.589138] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1231. [3.589630] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1232. [3.590197] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1233. [3.590645] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1234. [3.591190] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1235. [3.591731] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1236. [3.592376] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1237. [3.592919] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1238. [3.593579] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1239. [3.594046] HW.GFX.GMA.DP_Info.Read_Link_Status
  1240. [3.594375] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1241. [3.594753] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1242. [3.595264] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1243. [3.595808] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1244. [3.596252] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1245. [3.596780] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1246. [3.597322] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1247. [3.597951] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1248. [3.598482] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1249. [3.599033] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1250.  
  1251. [3.599583] Link Status:
  1252. [3.599749] Lane0:
  1253. [3.599884] CR_Done : 0
  1254. [3.600111] Channel_EQ_Done: 0
  1255. [3.600342] Symbol_Locked : 0
  1256. [3.600572] Lane1:
  1257. [3.600709] CR_Done : 0
  1258. [3.600938] Channel_EQ_Done: 0
  1259. [3.601171] Symbol_Locked : 0
  1260. [3.601401] Interlane_Align_Done: 0
  1261. [3.601652] Adjust0:
  1262. [3.601804] Voltage_Swing: 2
  1263. [3.602034] Pre_Emph : 0
  1264. [3.602267] Adjust1:
  1265. [3.602430] Voltage_Swing: 2
  1266. [3.602656] Pre_Emph : 0
  1267.  
  1268. [3.602907] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1269. [3.603307] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1270. [3.603853] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1271. [3.604292] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1272. [3.604797] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1273. [3.605312] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1274. [3.605852] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1275. [3.606329] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1276. [3.606705] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1277. [3.607213] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1278. [3.607736] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1279. [3.608279] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1280. [3.608703] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1281. [3.609216] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1282. [3.609726] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1283. [3.610355] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1284. [3.610866] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1285. [3.611475] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1286. [3.611974] HW.GFX.GMA.DP_Info.Read_Link_Status
  1287. [3.612291] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1288. [3.612688] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1289. [3.613195] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1290. [3.613754] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1291. [3.614160] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1292. [3.614648] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1293. [3.615165] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1294. [3.615733] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1295. [3.616273] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1296. [3.616779] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1297.  
  1298. [3.617354] Link Status:
  1299. [3.617527] Lane0:
  1300. [3.617667] CR_Done : 0
  1301. [3.617912] Channel_EQ_Done: 0
  1302. [3.618129] Symbol_Locked : 0
  1303. [3.618357] Lane1:
  1304. [3.618492] CR_Done : 0
  1305. [3.618738] Channel_EQ_Done: 0
  1306. [3.618971] Symbol_Locked : 0
  1307. [3.619212] Interlane_Align_Done: 0
  1308. [3.619434] Adjust0:
  1309. [3.619595] Voltage_Swing: 2
  1310. [3.619822] Pre_Emph : 0
  1311. [3.620036] Adjust1:
  1312. [3.620176] Voltage_Swing: 2
  1313. [3.620369] Pre_Emph : 0
  1314.  
  1315. [3.620590] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1316. [3.620981] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1317. [3.621515] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1318. [3.621967] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1319. [3.622510] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1320. [3.623052] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1321. [3.623596] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1322. [3.624113] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1323. [3.624513] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1324. [3.625060] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1325. [3.625633] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1326. [3.626170] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1327. [3.626579] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1328. [3.627119] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1329. [3.627659] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1330. [3.628295] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1331. [3.628796] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1332. [3.629399] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1333. [3.629870] HW.GFX.GMA.DP_Info.Read_Link_Status
  1334. [3.630169] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1335. [3.630604] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1336. [3.631089] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1337. [3.631625] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1338. [3.632021] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1339. [3.632495] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1340. [3.633034] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1341. [3.633668] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1342. [3.634224] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1343. [3.634787] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1344.  
  1345. [3.635373] Link Status:
  1346. [3.635555] Lane0:
  1347. [3.635702] CR_Done : 0
  1348. [3.635951] Channel_EQ_Done: 0
  1349. [3.636191] Symbol_Locked : 0
  1350. [3.636434] Lane1:
  1351. [3.636582] CR_Done : 0
  1352. [3.636830] Channel_EQ_Done: 0
  1353. [3.637065] Symbol_Locked : 0
  1354. [3.637308] Interlane_Align_Done: 0
  1355. [3.637574] Adjust0:
  1356. [3.637733] Voltage_Swing: 2
  1357. [3.637958] Pre_Emph : 0
  1358. [3.638189] Adjust1:
  1359. [3.638355] Voltage_Swing: 2
  1360. [3.638579] Pre_Emph : 0
  1361.  
  1362. [3.638838] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1363. [3.639244] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1364. [3.639748] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1365. [3.640149] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1366. [3.640629] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1367. [3.641200] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1368. [3.641672] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1369. [3.642121] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1370. [3.642527] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1371. [3.643069] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1372. [3.643638] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1373. [3.644197] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1374. [3.644647] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1375. [3.645191] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1376. [3.645733] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1377. [3.646364] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1378. [3.646911] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1379. [3.647577] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1380. [3.648076] HW.GFX.GMA.DP_Info.Read_Link_Status
  1381. [3.648398] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1382. [3.648794] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1383. [3.649264] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1384. [3.649829] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1385. [3.650279] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1386. [3.650825] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1387. [3.651366] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1388. [3.651963] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1389. [3.652504] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1390. [3.653069] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1391.  
  1392. [3.653618] Link Status:
  1393. [3.653775] Lane0:
  1394. [3.653923] CR_Done : 0
  1395. [3.654166] Channel_EQ_Done: 0
  1396. [3.654404] Symbol_Locked : 0
  1397. [3.654647] Lane1:
  1398. [3.654779] CR_Done : 0
  1399. [3.655038] Channel_EQ_Done: 0
  1400. [3.655269] Symbol_Locked : 0
  1401. [3.655510] Interlane_Align_Done: 0
  1402. [3.655763] Adjust0:
  1403. [3.655916] Voltage_Swing: 2
  1404. [3.656117] Pre_Emph : 0
  1405. [3.656350] Adjust1:
  1406. [3.656511] Voltage_Swing: 2
  1407. [3.656746] Pre_Emph : 0
  1408.  
  1409. [3.657004] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1410. [3.657523] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1411. [3.657925] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1412. [3.658431] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  1413. [3.658979] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1414. [3.659542] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1415. [3.659965] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1416. [3.660506] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  1417. [3.661041] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1418. [3.661616] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1419. [3.662160] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1420. [3.662728] HW.GFX.GMA.Registers.Write: 0x80040200 -> 0x00064040:DP_TP_CTL_A
  1421. [3.663259] HW.GFX.GMA.Registers.Write: 0x80040300 -> 0x00064040:DP_TP_CTL_A
  1422. [3.663779] HW.GFX.GMA.Connectors.DDI.Digital_Off
  1423. [3.664111] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1424. [3.664507] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1425. [3.665051] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DDI_BUF_CTL_A
  1426. [3.665547] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1427. [3.666091] HW.GFX.GMA.Registers.Write: 0x07000013 -> 0x00064000:DDI_BUF_CTL_A
  1428. [3.666634] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A
  1429. [3.667077] HW.GFX.GMA.Registers.Read: 0x80040300 <- 0x00064040:DP_TP_CTL_A
  1430. [3.667623] HW.GFX.GMA.Registers.Write: 0x00040300 -> 0x00064040:DP_TP_CTL_A
  1431. [3.668153] HW.GFX.GMA.Registers.Wait: 0x00000080 <- 0x00000080 & 0x00064000:DDI_BUF_CTL_A
  1432. [3.668754] HW.GFX.GMA.Registers.Set_Mask: 0x00008000 .S DPLL_CTRL2
  1433. [3.669162] HW.GFX.GMA.Registers.Read: 0x00af0003 <- 0x0006c05c:DPLL_CTRL2
  1434. [3.669682] HW.GFX.GMA.Registers.Write: 0x00af8003 -> 0x0006c05c:DPLL_CTRL2
  1435. [3.670212] HW.GFX.GMA.Connectors.Pre_On
  1436. [3.670484] HW.GFX.GMA.Connectors.DDI.Pre_On
  1437. [3.670794] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1438. [3.671215] HW.GFX.GMA.Registers.Read: 0x00af8003 <- 0x0006c05c:DPLL_CTRL2
  1439. [3.671743] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2
  1440. [3.672263] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1441. [3.672689] HW.GFX.GMA.Registers.Write: 0x80040080 -> 0x00064040:DP_TP_CTL_A
  1442. [3.673219] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1443. [3.673616] HW.GFX.GMA.Registers.Read: 0x07000093 <- 0x00064000:DDI_BUF_CTL_A
  1444. [3.674160] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1445. [3.674610] HW.GFX.GMA.Registers.Read: 0x07000093 <- 0x00064000:DDI_BUF_CTL_A
  1446. [3.675155] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1447. [3.675698] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1448. [3.676840] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1449. [3.677262] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1450. [3.677658] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1451. [3.678203] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1452. [3.678769] HW.GFX.GMA.Registers.Write: 0x0a820000 -> 0x00064018:DDI_AUX_DATA_A_2
  1453. [3.679326] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1454. [3.679743] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1455. [3.680284] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1456. [3.680814] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1457. [3.681448] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1458. [3.681972] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1459. [3.682536] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1460. [3.682932] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1461. [3.683468] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1462. [3.684023] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1463. [3.684580] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1464. [3.685010] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1465. [3.685544] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1466. [3.686082] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1467. [3.686692] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1468. [3.687213] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1469. [3.687741] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1470. [3.688277] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1471. [3.688671] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1472. [3.689181] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1473. [3.689743] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1474. [3.690284] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1475. [3.690728] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1476. [3.691257] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1477. [3.691759] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1478. [3.692352] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1479. [3.692866] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1480. [3.693506] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1481. [3.694005] HW.GFX.GMA.DP_Info.Read_Link_Status
  1482. [3.694324] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1483. [3.694721] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1484. [3.695264] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1485. [3.695829] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1486. [3.696277] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1487. [3.696822] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1488. [3.697364] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1489. [3.698005] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1490. [3.698550] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1491. [3.699097] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1492.  
  1493. [3.699680] Link Status:
  1494. [3.699849] Lane0:
  1495. [3.699997] CR_Done : 0
  1496. [3.700244] Channel_EQ_Done: 0
  1497. [3.700484] Symbol_Locked : 0
  1498. [3.700727] Lane1:
  1499. [3.700877] CR_Done : 0
  1500. [3.701134] Channel_EQ_Done: 0
  1501. [3.701365] Symbol_Locked : 0
  1502. [3.701605] Interlane_Align_Done: 0
  1503. [3.701865] Adjust0:
  1504. [3.702028] Voltage_Swing: 1
  1505. [3.702255] Pre_Emph : 0
  1506. [3.702487] Adjust1:
  1507. [3.702647] Voltage_Swing: 1
  1508. [3.702874] Pre_Emph : 0
  1509.  
  1510. [3.703141] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1511. [3.703537] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1512. [3.704079] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1513. [3.704533] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1514. [3.705073] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1515. [3.705616] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1516. [3.706160] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1517. [3.706661] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1518. [3.707057] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1519. [3.707601] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1520. [3.708168] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1521. [3.708746] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1522. [3.709196] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1523. [3.709742] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1524. [3.710281] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1525. [3.710916] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1526. [3.711462] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1527. [3.712110] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1528. [3.712610] HW.GFX.GMA.DP_Info.Read_Link_Status
  1529. [3.712930] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1530. [3.713330] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1531. [3.713870] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1532. [3.714431] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1533. [3.714885] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1534. [3.715439] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1535. [3.715982] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1536. [3.716616] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1537. [3.717152] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1538. [3.717722] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1539.  
  1540. [3.718314] Link Status:
  1541. [3.718489] Lane0:
  1542. [3.718630] CR_Done : 0
  1543. [3.718878] Channel_EQ_Done: 0
  1544. [3.719127] Symbol_Locked : 0
  1545. [3.719370] Lane1:
  1546. [3.719519] CR_Done : 0
  1547. [3.719767] Channel_EQ_Done: 0
  1548. [3.720008] Symbol_Locked : 0
  1549. [3.720254] Interlane_Align_Done: 0
  1550. [3.720512] Adjust0:
  1551. [3.720675] Voltage_Swing: 2
  1552. [3.720912] Pre_Emph : 0
  1553. [3.721144] Adjust1:
  1554. [3.721303] Voltage_Swing: 2
  1555. [3.721530] Pre_Emph : 0
  1556.  
  1557. [3.721785] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1558. [3.722184] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1559. [3.722742] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1560. [3.723192] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1561. [3.723738] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1562. [3.724281] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1563. [3.724826] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1564. [3.725338] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1565. [3.725739] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1566. [3.726290] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1567. [3.726855] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1568. [3.727420] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1569. [3.727874] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1570. [3.728414] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1571. [3.728960] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1572. [3.729577] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1573. [3.730119] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1574. [3.730791] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1575. [3.731299] HW.GFX.GMA.DP_Info.Read_Link_Status
  1576. [3.731614] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1577. [3.732020] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1578. [3.732565] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1579. [3.733127] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1580. [3.733577] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1581. [3.734122] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1582. [3.734664] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1583. [3.735308] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1584. [3.735857] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1585. [3.736420] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1586.  
  1587. [3.737009] Link Status:
  1588. [3.737193] Lane0:
  1589. [3.737341] CR_Done : 0
  1590. [3.737592] Channel_EQ_Done: 0
  1591. [3.737829] Symbol_Locked : 0
  1592. [3.738070] Lane1:
  1593. [3.738218] CR_Done : 0
  1594. [3.738467] Channel_EQ_Done: 0
  1595. [3.738706] Symbol_Locked : 0
  1596. [3.738955] Interlane_Align_Done: 0
  1597. [3.739210] Adjust0:
  1598. [3.739372] Voltage_Swing: 2
  1599. [3.739599] Pre_Emph : 0
  1600. [3.739831] Adjust1:
  1601. [3.739993] Voltage_Swing: 2
  1602. [3.740217] Pre_Emph : 0
  1603.  
  1604. [3.740478] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1605. [3.740879] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1606. [3.741421] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1607. [3.741875] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1608. [3.742416] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1609. [3.742967] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1610. [3.743509] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1611. [3.744006] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1612. [3.744408] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1613. [3.744876] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1614. [3.745366] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1615. [3.745863] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1616. [3.746281] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1617. [3.746784] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1618. [3.747252] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1619. [3.747806] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1620. [3.748333] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1621. [3.748988] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1622. [3.749480] HW.GFX.GMA.DP_Info.Read_Link_Status
  1623. [3.749806] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1624. [3.750205] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1625. [3.750753] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1626. [3.751313] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1627. [3.751769] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1628. [3.752312] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1629. [3.752856] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1630. [3.753487] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1631. [3.754031] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1632. [3.754606] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1633.  
  1634. [3.755196] Link Status:
  1635. [3.755368] Lane0:
  1636. [3.755517] CR_Done : 0
  1637. [3.755729] Channel_EQ_Done: 0
  1638. [3.755936] Symbol_Locked : 0
  1639. [3.756142] Lane1:
  1640. [3.756282] CR_Done : 0
  1641. [3.756494] Channel_EQ_Done: 0
  1642. [3.756736] Symbol_Locked : 0
  1643. [3.756979] Interlane_Align_Done: 0
  1644. [3.757235] Adjust0:
  1645. [3.757396] Voltage_Swing: 2
  1646. [3.757621] Pre_Emph : 0
  1647. [3.757852] Adjust1:
  1648. [3.758014] Voltage_Swing: 2
  1649. [3.758250] Pre_Emph : 0
  1650.  
  1651. [3.758506] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1652. [3.758905] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1653. [3.759453] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1654. [3.759904] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1655. [3.760449] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1656. [3.760990] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1657. [3.761534] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1658. [3.762044] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1659. [3.762443] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1660. [3.762939] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1661. [3.763426] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1662. [3.763984] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1663. [3.764439] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1664. [3.764981] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1665. [3.765534] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1666. [3.766168] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1667. [3.766715] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1668. [3.767380] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1669. [3.767884] HW.GFX.GMA.DP_Info.Read_Link_Status
  1670. [3.768202] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1671. [3.768602] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1672. [3.769160] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1673. [3.769728] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1674. [3.770146] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1675. [3.770615] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1676. [3.771154] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1677. [3.771787] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1678. [3.772328] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1679. [3.772894] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1680.  
  1681. [3.773481] Link Status:
  1682. [3.773654] Lane0:
  1683. [3.773803] CR_Done : 0
  1684. [3.774058] Channel_EQ_Done: 0
  1685. [3.774297] Symbol_Locked : 0
  1686. [3.774538] Lane1:
  1687. [3.774685] CR_Done : 0
  1688. [3.774934] Channel_EQ_Done: 0
  1689. [3.775171] Symbol_Locked : 0
  1690. [3.775412] Interlane_Align_Done: 0
  1691. [3.775669] Adjust0:
  1692. [3.775838] Voltage_Swing: 2
  1693. [3.776062] Pre_Emph : 0
  1694. [3.776297] Adjust1:
  1695. [3.776456] Voltage_Swing: 2
  1696. [3.776683] Pre_Emph : 0
  1697.  
  1698. [3.776942] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1699. [3.777338] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1700. [3.777808] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1701. [3.778263] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1702. [3.778806] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1703. [3.779361] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1704. [3.779903] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1705. [3.780410] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1706. [3.780809] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1707. [3.781349] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1708. [3.781915] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1709. [3.782482] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1710. [3.782932] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1711. [3.783475] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1712. [3.784017] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1713. [3.784646] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1714. [3.785123] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1715. [3.785788] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1716. [3.786286] HW.GFX.GMA.DP_Info.Read_Link_Status
  1717. [3.786616] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1718. [3.787012] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1719. [3.787558] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1720. [3.788114] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1721. [3.788567] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1722. [3.789110] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1723. [3.789655] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1724. [3.790284] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1725. [3.790829] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1726. [3.791397] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1727.  
  1728. [3.791943] Link Status:
  1729. [3.792094] Lane0:
  1730. [3.792223] CR_Done : 0
  1731. [3.792433] Channel_EQ_Done: 0
  1732. [3.792641] Symbol_Locked : 0
  1733. [3.792885] Lane1:
  1734. [3.793034] CR_Done : 0
  1735. [3.793283] Channel_EQ_Done: 0
  1736. [3.793532] Symbol_Locked : 0
  1737. [3.793776] Interlane_Align_Done: 0
  1738. [3.794032] Adjust0:
  1739. [3.794196] Voltage_Swing: 2
  1740. [3.794421] Pre_Emph : 0
  1741. [3.794653] Adjust1:
  1742. [3.794813] Voltage_Swing: 2
  1743. [3.795040] Pre_Emph : 0
  1744.  
  1745. [3.795297] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1746. [3.795702] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1747. [3.796246] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1748. [3.796696] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1749. [3.797238] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1750. [3.797780] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1751. [3.798316] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1752. [3.798828] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1753. [3.799234] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1754. [3.799704] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1755. [3.800195] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1756. [3.800761] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1757. [3.801218] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1758. [3.801764] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1759. [3.802319] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1760. [3.802957] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1761. [3.803505] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1762. [3.804175] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1763. [3.804688] HW.GFX.GMA.DP_Info.Read_Link_Status
  1764. [3.805008] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1765. [3.805409] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1766. [3.805955] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1767. [3.806529] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1768. [3.806929] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1769. [3.807398] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1770. [3.807935] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1771. [3.808571] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1772. [3.809116] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1773. [3.809682] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1774.  
  1775. [3.810274] Link Status:
  1776. [3.810448] Lane0:
  1777. [3.810598] CR_Done : 0
  1778. [3.810849] Channel_EQ_Done: 0
  1779. [3.811088] Symbol_Locked : 0
  1780. [3.811342] Lane1:
  1781. [3.811493] CR_Done : 0
  1782. [3.811742] Channel_EQ_Done: 0
  1783. [3.811983] Symbol_Locked : 0
  1784. [3.812229] Interlane_Align_Done: 0
  1785. [3.812486] Adjust0:
  1786. [3.812650] Voltage_Swing: 2
  1787. [3.812882] Pre_Emph : 0
  1788. [3.813129] Adjust1:
  1789. [3.813292] Voltage_Swing: 2
  1790. [3.813516] Pre_Emph : 0
  1791.  
  1792. [3.813772] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1793. [3.814238] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1794. [3.814583] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1795. [3.815123] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  1796. [3.815689] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1797. [3.816256] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1798. [3.816704] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1799. [3.817245] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  1800. [3.817786] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1801. [3.818426] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1802. [3.818971] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1803. [3.819539] HW.GFX.GMA.Registers.Write: 0x80040200 -> 0x00064040:DP_TP_CTL_A
  1804. [3.820069] HW.GFX.GMA.Registers.Write: 0x80040300 -> 0x00064040:DP_TP_CTL_A
  1805. [3.820607] HW.GFX.GMA.Connectors.DDI.Digital_Off
  1806. [3.820940] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1807. [3.821339] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1808. [3.821812] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DDI_BUF_CTL_A
  1809. [3.822257] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1810. [3.822802] HW.GFX.GMA.Registers.Write: 0x07000013 -> 0x00064000:DDI_BUF_CTL_A
  1811. [3.823350] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A
  1812. [3.823825] HW.GFX.GMA.Registers.Read: 0x80040300 <- 0x00064040:DP_TP_CTL_A
  1813. [3.824357] HW.GFX.GMA.Registers.Write: 0x00040300 -> 0x00064040:DP_TP_CTL_A
  1814. [3.824889] HW.GFX.GMA.Registers.Wait: 0x00000080 <- 0x00000080 & 0x00064000:DDI_BUF_CTL_A
  1815. [3.825536] HW.GFX.GMA.Registers.Set_Mask: 0x00008000 .S DPLL_CTRL2
  1816. [3.826003] HW.GFX.GMA.Registers.Read: 0x00af0003 <- 0x0006c05c:DPLL_CTRL2
  1817. [3.826527] HW.GFX.GMA.Registers.Write: 0x00af8003 -> 0x0006c05c:DPLL_CTRL2
  1818. [3.827053] HW.GFX.GMA.PLLs.Free
  1819. [3.827288] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL2_CTL
  1820. [3.827767] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00046014:LCPLL2_CTL
  1821. [3.828292] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046014:LCPLL2_CTL
  1822. [3.828816] HW.GFX.GMA.Connector_Info.Next_Link_Setting
  1823. [3.829149] Trying DP settings: Symbol Rate = 162000000; Lane Count = 2
  1824.  
  1825. [3.829597] HW.GFX.GMA.PLLs.Alloc
  1826. [3.829827] HW.GFX.GMA.Registers.Read: 0x000000c0 <- 0x0006c058:DPLL_CTRL1
  1827. [3.830345] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1
  1828. [3.830779] HW.GFX.GMA.Registers.Read: 0x000000c0 <- 0x0006c058:DPLL_CTRL1
  1829. [3.831302] HW.GFX.GMA.Registers.Write: 0x00000140 -> 0x0006c058:DPLL_CTRL1
  1830. [3.831822] HW.GFX.GMA.Registers.Read: 0x00000140 <- 0x0006c058:DPLL_CTRL1
  1831. [3.832351] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL
  1832. [3.832883] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS
  1833. [3.833512] HW.GFX.GMA.Connectors.Pre_On
  1834. [3.833783] HW.GFX.GMA.Connectors.DDI.Pre_On
  1835. [3.834080] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1836. [3.834515] HW.GFX.GMA.Registers.Read: 0x00af8003 <- 0x0006c05c:DPLL_CTRL2
  1837. [3.835040] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2
  1838. [3.835564] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1839. [3.835993] HW.GFX.GMA.Registers.Write: 0x80040080 -> 0x00064040:DP_TP_CTL_A
  1840. [3.836502] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1841. [3.836847] HW.GFX.GMA.Registers.Read: 0x07000093 <- 0x00064000:DDI_BUF_CTL_A
  1842. [3.837332] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1843. [3.837784] HW.GFX.GMA.Registers.Read: 0x07000093 <- 0x00064000:DDI_BUF_CTL_A
  1844. [3.838329] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1845. [3.838871] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1846. [3.840026] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1847. [3.840448] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1848. [3.840846] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1849. [3.841398] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1850. [3.841961] HW.GFX.GMA.Registers.Write: 0x06820000 -> 0x00064018:DDI_AUX_DATA_A_2
  1851. [3.842529] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1852. [3.842981] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1853. [3.843530] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1854. [3.844061] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1855. [3.844606] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1856. [3.845148] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1857. [3.845726] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1858. [3.846122] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1859. [3.846668] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1860. [3.847232] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1861. [3.847796] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1862. [3.848248] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1863. [3.848804] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1864. [3.849350] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1865. [3.849985] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1866. [3.850525] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1867. [3.851102] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1868. [3.851578] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1869. [3.851922] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1870. [3.852461] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1871. [3.853030] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1872. [3.853595] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1873. [3.854046] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1874. [3.854592] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1875. [3.855130] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1876. [3.855766] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1877. [3.856322] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1878. [3.856985] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1879. [3.857489] HW.GFX.GMA.DP_Info.Read_Link_Status
  1880. [3.857817] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1881. [3.858213] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1882. [3.858758] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1883. [3.859248] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1884. [3.859683] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1885. [3.860230] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1886. [3.860776] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1887. [3.861406] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1888. [3.861952] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1889. [3.862519] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1890.  
  1891. [3.863106] Link Status:
  1892. [3.863278] Lane0:
  1893. [3.863428] CR_Done : 0
  1894. [3.863674] Channel_EQ_Done: 0
  1895. [3.863915] Symbol_Locked : 0
  1896. [3.864155] Lane1:
  1897. [3.864302] CR_Done : 0
  1898. [3.864551] Channel_EQ_Done: 0
  1899. [3.864798] Symbol_Locked : 0
  1900. [3.865037] Interlane_Align_Done: 0
  1901. [3.865297] Adjust0:
  1902. [3.865457] Voltage_Swing: 1
  1903. [3.865681] Pre_Emph : 0
  1904. [3.865913] Adjust1:
  1905. [3.866073] Voltage_Swing: 1
  1906. [3.866273] Pre_Emph : 0
  1907.  
  1908. [3.866493] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1909. [3.866849] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1910. [3.867393] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1911. [3.867850] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1912. [3.868394] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1913. [3.868935] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1914. [3.869477] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1915. [3.869992] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1916. [3.870398] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1917. [3.870942] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1918. [3.871505] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1919. [3.872070] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1920. [3.872520] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1921. [3.873064] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1922. [3.873572] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1923. [3.874114] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1924. [3.874656] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1925. [3.875321] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1926. [3.875820] HW.GFX.GMA.DP_Info.Read_Link_Status
  1927. [3.876138] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1928. [3.876534] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1929. [3.877079] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1930. [3.877650] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1931. [3.878105] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1932. [3.878648] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1933. [3.879190] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1934. [3.879830] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1935. [3.880375] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1936. [3.880917] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1937.  
  1938. [3.881430] Link Status:
  1939. [3.881582] Lane0:
  1940. [3.881711] CR_Done : 0
  1941. [3.881959] Channel_EQ_Done: 0
  1942. [3.882202] Symbol_Locked : 0
  1943. [3.882456] Lane1:
  1944. [3.882605] CR_Done : 0
  1945. [3.882856] Channel_EQ_Done: 0
  1946. [3.883097] Symbol_Locked : 0
  1947. [3.883341] Interlane_Align_Done: 0
  1948. [3.883595] Adjust0:
  1949. [3.883757] Voltage_Swing: 2
  1950. [3.883982] Pre_Emph : 0
  1951. [3.884214] Adjust1:
  1952. [3.884389] Voltage_Swing: 2
  1953. [3.884616] Pre_Emph : 0
  1954.  
  1955. [3.884874] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1956. [3.885274] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1957. [3.885819] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1958. [3.886268] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1959. [3.886814] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  1960. [3.887356] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  1961. [3.887910] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1962. [3.888361] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1963. [3.888708] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1964. [3.889254] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1965. [3.889817] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  1966. [3.890383] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1967. [3.890840] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1968. [3.891383] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1969. [3.891929] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1970. [3.892564] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1971. [3.893119] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1972. [3.893786] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1973. [3.894296] HW.GFX.GMA.DP_Info.Read_Link_Status
  1974. [3.894613] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1975. [3.895019] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1976. [3.895522] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1977. [3.896012] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1978. [3.896463] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1979. [3.897005] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1980. [3.897548] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1981. [3.898182] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1982. [3.898728] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1983. [3.899293] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  1984.  
  1985. [3.899883] Link Status:
  1986. [3.900056] Lane0:
  1987. [3.900216] CR_Done : 0
  1988. [3.900464] Channel_EQ_Done: 0
  1989. [3.900705] Symbol_Locked : 0
  1990. [3.900947] Lane1:
  1991. [3.901098] CR_Done : 0
  1992. [3.901347] Channel_EQ_Done: 0
  1993. [3.901590] Symbol_Locked : 0
  1994. [3.901832] Interlane_Align_Done: 0
  1995. [3.902099] Adjust0:
  1996. [3.902261] Voltage_Swing: 2
  1997. [3.902493] Pre_Emph : 0
  1998. [3.902728] Adjust1:
  1999. [3.902866] Voltage_Swing: 2
  2000. [3.903060] Pre_Emph : 0
  2001.  
  2002. [3.903282] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  2003. [3.903681] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2004. [3.904222] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  2005. [3.904679] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2006. [3.905222] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  2007. [3.905765] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2008. [3.906308] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  2009. [3.906828] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2010. [3.907229] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2011. [3.907767] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  2012. [3.908330] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  2013. [3.908899] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2014. [3.909352] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2015. [3.909897] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  2016. [3.910366] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2017. [3.910923] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2018. [3.911470] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  2019. [3.912136] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  2020. [3.912648] HW.GFX.GMA.DP_Info.Read_Link_Status
  2021. [3.912970] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2022. [3.913373] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2023. [3.913918] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  2024. [3.914491] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2025. [3.914949] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2026. [3.915494] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  2027. [3.916037] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2028. [3.916679] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2029. [3.917224] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  2030. [3.917713] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  2031.  
  2032. [3.918226] Link Status:
  2033. [3.918404] Lane0:
  2034. [3.918555] CR_Done : 0
  2035. [3.918803] Channel_EQ_Done: 0
  2036. [3.919046] Symbol_Locked : 0
  2037. [3.919293] Lane1:
  2038. [3.919440] CR_Done : 0
  2039. [3.919689] Channel_EQ_Done: 0
  2040. [3.919935] Symbol_Locked : 0
  2041. [3.920178] Interlane_Align_Done: 0
  2042. [3.920435] Adjust0:
  2043. [3.920596] Voltage_Swing: 2
  2044. [3.920823] Pre_Emph : 0
  2045. [3.921056] Adjust1:
  2046. [3.921221] Voltage_Swing: 2
  2047. [3.921445] Pre_Emph : 0
  2048.  
  2049. [3.921711] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  2050. [3.922108] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2051. [3.922654] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  2052. [3.923110] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2053. [3.923653] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  2054. [3.924193] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2055. [3.924713] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  2056. [3.925156] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2057. [3.925500] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2058. [3.926044] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  2059. [3.926613] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  2060. [3.927174] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2061. [3.927631] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2062. [3.928176] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  2063. [3.928717] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2064. [3.929348] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2065. [3.929888] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  2066. [3.930552] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  2067. [3.931058] HW.GFX.GMA.DP_Info.Read_Link_Status
  2068. [3.931378] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2069. [3.931775] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2070. [3.932242] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  2071. [3.932734] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2072. [3.933182] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2073. [3.933727] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  2074. [3.934274] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2075. [3.934906] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2076. [3.935451] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  2077. [3.936026] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  2078.  
  2079. [3.936613] Link Status:
  2080. [3.936782] Lane0:
  2081. [3.936930] CR_Done : 0
  2082. [3.937175] Channel_EQ_Done: 0
  2083. [3.937424] Symbol_Locked : 0
  2084. [3.937663] Lane1:
  2085. [3.937810] CR_Done : 0
  2086. [3.938062] Channel_EQ_Done: 0
  2087. [3.938302] Symbol_Locked : 0
  2088. [3.938542] Interlane_Align_Done: 0
  2089. [3.938800] Adjust0:
  2090. [3.938962] Voltage_Swing: 2
  2091. [3.939186] Pre_Emph : 0
  2092. [3.939396] Adjust1:
  2093. [3.939536] Voltage_Swing: 2
  2094. [3.939732] Pre_Emph : 0
  2095.  
  2096. [3.939954] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  2097. [3.940351] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2098. [3.940896] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  2099. [3.941349] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2100. [3.941897] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  2101. [3.942438] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2102. [3.942981] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  2103. [3.943497] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2104. [3.943893] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2105. [3.944438] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  2106. [3.945013] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  2107. [3.945582] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2108. [3.946033] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2109. [3.946578] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  2110. [3.947049] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2111. [3.947680] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2112. [3.948221] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  2113. [3.948891] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  2114. [3.949389] HW.GFX.GMA.DP_Info.Read_Link_Status
  2115. [3.949707] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2116. [3.950113] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2117. [3.950657] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  2118. [3.951219] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2119. [3.951670] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2120. [3.952212] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  2121. [3.952757] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2122. [3.953401] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2123. [3.953920] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  2124. [3.954410] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  2125.  
  2126. [3.954999] Link Status:
  2127. [3.955181] Lane0:
  2128. [3.955331] CR_Done : 0
  2129. [3.955578] Channel_EQ_Done: 0
  2130. [3.955817] Symbol_Locked : 0
  2131. [3.956060] Lane1:
  2132. [3.956210] CR_Done : 0
  2133. [3.956462] Channel_EQ_Done: 0
  2134. [3.956703] Symbol_Locked : 0
  2135. [3.956946] Interlane_Align_Done: 0
  2136. [3.957211] Adjust0:
  2137. [3.957373] Voltage_Swing: 2
  2138. [3.957598] Pre_Emph : 0
  2139. [3.957830] Adjust1:
  2140. [3.957990] Voltage_Swing: 2
  2141. [3.958214] Pre_Emph : 0
  2142.  
  2143. [3.958472] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  2144. [3.958879] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2145. [3.959425] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  2146. [3.959876] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2147. [3.960420] HW.GFX.GMA.Registers.Write: 0x87000013 -> 0x00064000:DDI_BUF_CTL_A
  2148. [3.960957] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2149. [3.961469] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  2150. [3.961945] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2151. [3.962301] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2152. [3.962774] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  2153. [3.963328] HW.GFX.GMA.Registers.Write: 0x06060000 -> 0x00064018:DDI_AUX_DATA_A_2
  2154. [3.963892] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2155. [3.964342] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2156. [3.964888] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  2157. [3.965433] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2158. [3.966063] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2159. [3.966609] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  2160. [3.967276] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  2161. [3.967779] HW.GFX.GMA.DP_Info.Read_Link_Status
  2162. [3.968095] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2163. [3.968491] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2164. [3.969035] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  2165. [3.969598] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2166. [3.969993] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2167. [3.970465] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  2168. [3.971018] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2169. [3.971654] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2170. [3.972199] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  2171. [3.972762] HW.GFX.GMA.Registers.Read: 0x00220000 <- 0x00064018:DDI_AUX_DATA_A_2
  2172.  
  2173. [3.973351] Link Status:
  2174. [3.973524] Lane0:
  2175. [3.973671] CR_Done : 0
  2176. [3.973920] Channel_EQ_Done: 0
  2177. [3.974158] Symbol_Locked : 0
  2178. [3.974397] Lane1:
  2179. [3.974545] CR_Done : 0
  2180. [3.974801] Channel_EQ_Done: 0
  2181. [3.975044] Symbol_Locked : 0
  2182. [3.975284] Interlane_Align_Done: 0
  2183. [3.975540] Adjust0:
  2184. [3.975705] Voltage_Swing: 2
  2185. [3.975934] Pre_Emph : 0
  2186. [3.976168] Adjust1:
  2187. [3.976330] Voltage_Swing: 2
  2188. [3.976565] Pre_Emph : 0
  2189.  
  2190. [3.976821] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  2191. [3.977283] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  2192. [3.977627] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2193. [3.978181] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  2194. [3.978746] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  2195. [3.979313] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  2196. [3.979762] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  2197. [3.980305] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  2198. [3.980852] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  2199. [3.981485] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  2200. [3.982028] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  2201. [3.982597] HW.GFX.GMA.Registers.Write: 0x80040200 -> 0x00064040:DP_TP_CTL_A
  2202. [3.983125] HW.GFX.GMA.Registers.Write: 0x80040300 -> 0x00064040:DP_TP_CTL_A
  2203. [3.983651] HW.GFX.GMA.Connectors.DDI.Digital_Off
  2204. [3.983983] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  2205. [3.984362] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2206. [3.984828] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DDI_BUF_CTL_A
  2207. [3.985324] HW.GFX.GMA.Registers.Read: 0x87000013 <- 0x00064000:DDI_BUF_CTL_A
  2208. [3.985868] HW.GFX.GMA.Registers.Write: 0x07000013 -> 0x00064000:DDI_BUF_CTL_A
  2209. [3.986409] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A
  2210. [3
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