library     IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_std.all;

entity Rest is
    port(E: in std_logic;
    CLK: in std_logic;
    tip: in std_logic_vector(2 downto 0);
    --Banc: in std_logic_vector(7 downto 0);
    SumaIn: in std_logic_vector(7 downto 0);
    nr_banc: out std_logic_vector(7 downto 0);
    REST: out std_logic_vector(15 downto 0));
end Rest;

architecture Arch_Rest of Rest is
signal valoare : std_logic_vector(7 downto 0);
begin
    process(CLK,SumaIN,tip)
    variable b: std_logic_vector(7 downto 0);
	variable R: std_logic_vector(15 downto 0);
    begin
		if E = '1' then
			case tip is
				when "111" => valoare <= "00110010";
				when "110" => valoare <= "00010100";
				when "101" => valoare <= "00001010";
				when "100" => valoare <= "00000101";
				when "011" => valoare <= "00000010";
				when "010" => valoare <= "00000001";
				when others => NULL;
			end case;
                if std_logic_vector(unsigned(SumaIn) / unsigned(valoare)) > "00000000" then
					b := std_logic_vector(unsigned(SumaIn) / unsigned(valoare));
					R := std_logic_vector(unsigned(SumaIn) - unsigned(b) * unsigned(valoare));
                else
                    R := "0000000000000000";
					b := "00000000";
                end if;
            end if;
            nr_banc <= b;
            REST <=R;
    end process;
end Arch_Rest;