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-- Company:
-- Engineer:
--
-- Create Date: 06.12.2018 18:37:00
-- Design Name:
-- Module Name: Full_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Full_adder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           s : out STD_LOGIC;
           cout : out STD_LOGIC);
end Full_adder;

architecture Behavioral of Full_adder is

signal s2, c2, c1 : std_logic;
begin

HA1: entity work.half_adder port map (
    a => cin,
    b => s2,
    c => c1,
    s => s
);


HA2: entity work.half_adder port map(
    a => a,
    b => b,
    s => s2,
    c => c2
);

cout <= c1 or c2;


end Behavioral;