diff --git a/drivers/pwm/pwm-airoha.c b/drivers/pwm/pwm-airoha.c
index 4fe55e756839..026f41a5077e 100644
--- a/drivers/pwm/pwm-airoha.c
+++ b/drivers/pwm/pwm-airoha.c
@@ -37,7 +37,12 @@
 #define SERIAL_GPIO_FLASH_MODE_MASK    BIT(1)
 #define SERIAL_GPIO_MODE_74HC164_MASK  BIT(0)

-#define REG_GPIO_FLASH_PRD_SET(_n) (0x003c + (((_n) / 2) * 4))
+#define REG_GPIO_FLASH_PRD_SET(_n) (0x003c + (((_n) >> 1) << 2))
+#define GPIO_FLASH_PRD_HIGH_MASK(_n)   \
+   GENMASK(7 + (((_n) % 2) << 4),  ((_n) % 2) << 4)
+#define GPIO_FLASH_PRD_LOW_MASK(_n)    \
+   GENMASK(15 + (((_n) % 2) << 4), 8 + (((_n) % 2) << 4))
+
 /* Each flash period reg have up to 2 config */
 #define GPIO_FLASH_PRD_LOW_PRD     GENMASK(15, 8)
 #define GPIO_FLASH_PRD_HIGH_PRD        GENMASK(7, 0)
@@ -69,6 +74,9 @@
 #define AIROHA_PWM_NUM_SIPO        17
 #define AIROHA_PWM_MAX_CHANNELS        (AIROHA_PWM_NUM_GPIO + AIROHA_PWM_NUM_SIPO)

+#define AIROHA_PWM_FIELD_GET(mask, val)    (((val) & (mask)) >> __ffs(mask))
+#define AIROHA_PWM_FIELD_SET(mask, val)    (((val) << __ffs(mask)) & (mask))
+
 struct airoha_pwm_bucket {
    /* Bitmask of PWM channels using this bucket */
    u64 used;
@@ -231,7 +239,6 @@ static void airoha_pwm_calc_bucket_config(struct airoha_pwm *pc, int bucket,
                      u64 duty_ns, u64 period_ns)
 {
    u32 period_tick, duty_tick, mask, val;
-   u32 duty_val;

    duty_tick = airoha_pwm_get_duty_tick_from_ns(duty_ns, period_ns);
    period_tick = mul_u64_u64_div_u64(period_ns, AIROHA_PWM_PERIOD_MAX,
@@ -245,13 +252,15 @@ static void airoha_pwm_calc_bucket_config(struct airoha_pwm *pc, int bucket,
               mask, val);

    /* Configure duty cycle */
-   duty_val = FIELD_PREP(GPIO_FLASH_PRD_HIGH_PRD, duty_tick) |
-          FIELD_PREP(GPIO_FLASH_PRD_LOW_PRD,
-                 AIROHA_PWM_DUTY_FULL - duty_tick);
-   mask = GPIO_FLASH_PRD << GPIO_FLASH_PRD_SHIFT(bucket);
-   val = duty_val << GPIO_FLASH_PRD_SHIFT(bucket);
+   val = AIROHA_PWM_FIELD_SET(GPIO_FLASH_PRD_HIGH_MASK(bucket),
+                  duty_tick);
    regmap_update_bits(pc->regmap, REG_GPIO_FLASH_PRD_SET(bucket),
-              mask, val);
+              GPIO_FLASH_PRD_HIGH_MASK(bucket), val);
+
+   val = AIROHA_PWM_FIELD_SET(GPIO_FLASH_PRD_LOW_MASK(bucket),
+                  AIROHA_PWM_DUTY_FULL - duty_tick);
+   regmap_update_bits(pc->regmap, REG_GPIO_FLASH_PRD_SET(bucket),
+              GPIO_FLASH_PRD_LOW_MASK(bucket), val);
 }

 static void airoha_pwm_config_flash_map(struct airoha_pwm *pc,
@@ -350,11 +359,9 @@ static int airoha_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
                struct pwm_state *state)
 {
    struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
-   u32 period_tick, duty_tick;
-   int hwpwm = pwm->hwpwm;
-   u32 addr, val;
+   u32 period_tick, duty_tick, addr, val;
+   int ret, hwpwm = pwm->hwpwm;
    u8 bucket;
-   int ret;

    if (hwpwm < AIROHA_PWM_NUM_GPIO) {
        addr = REG_GPIO_FLASH_MAP(hwpwm);
@@ -389,8 +396,8 @@ static int airoha_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
    if (ret)
        return ret;

-   duty_tick = FIELD_GET(GPIO_FLASH_PRD_HIGH_PRD,
-                 val << GPIO_FLASH_PRD_SHIFT(bucket));
+   duty_tick = AIROHA_PWM_FIELD_GET(GPIO_FLASH_PRD_HIGH_MASK(bucket),
+                    val);
    state->duty_cycle = mul_u64_u64_div_u64(duty_tick, state->period,
                        AIROHA_PWM_DUTY_FULL);