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Benettig
Nov 1st, 2017
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  1. /*
  2. * Copyright 2013 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44.  
  45. #include "skeleton.dtsi"
  46.  
  47. #include <dt-bindings/interrupt-controller/arm-gic.h>
  48. #include <dt-bindings/thermal/thermal.h>
  49. #include <dt-bindings/dma/sun4i-a10.h>
  50. #include <dt-bindings/clock/sun4i-a10-ccu.h>
  51. #include <dt-bindings/reset/sun4i-a10-ccu.h>
  52.  
  53. / {
  54. interrupt-parent = <&gic>;
  55.  
  56. aliases {
  57. ethernet0 = &gmac;
  58. };
  59.  
  60. chosen {
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. ranges;
  64.  
  65. framebuffer@0 {
  66. compatible = "allwinner,simple-framebuffer",
  67. "simple-framebuffer";
  68. allwinner,pipeline = "de_be0-lcd0-hdmi";
  69. clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70. <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71. <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72. <&ccu CLK_HDMI>;
  73. status = "disabled";
  74. };
  75.  
  76. framebuffer@1 {
  77. compatible = "allwinner,simple-framebuffer",
  78. "simple-framebuffer";
  79. allwinner,pipeline = "de_be0-lcd0";
  80. clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81. <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82. <&ccu CLK_DRAM_DE_BE0>;
  83. status = "disabled";
  84. };
  85.  
  86. framebuffer@2 {
  87. compatible = "allwinner,simple-framebuffer",
  88. "simple-framebuffer";
  89. allwinner,pipeline = "de_be0-lcd0-tve0";
  90. clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91. <&ccu CLK_AHB_DE_BE0>,
  92. <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93. <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94. status = "disabled";
  95. };
  96. };
  97.  
  98. cpus {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101.  
  102. cpu0: cpu@0 {
  103. compatible = "arm,cortex-a7";
  104. device_type = "cpu";
  105. reg = <0>;
  106. clocks = <&ccu CLK_CPU>;
  107. clock-latency = <244144>; /* 8 32k periods */
  108. operating-points = <
  109. /* kHz uV */
  110. 960000 1400000
  111. 912000 1400000
  112. 864000 1300000
  113. 720000 1200000
  114. 528000 1100000
  115. 312000 1000000
  116. 144000 1000000
  117. >;
  118. #cooling-cells = <2>;
  119. cooling-min-level = <0>;
  120. cooling-max-level = <6>;
  121. };
  122.  
  123. cpu@1 {
  124. compatible = "arm,cortex-a7";
  125. device_type = "cpu";
  126. reg = <1>;
  127. };
  128. };
  129.  
  130. thermal-zones {
  131. cpu_thermal {
  132. /* milliseconds */
  133. polling-delay-passive = <250>;
  134. polling-delay = <1000>;
  135. thermal-sensors = <&rtp>;
  136.  
  137. cooling-maps {
  138. map0 {
  139. trip = <&cpu_alert0>;
  140. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  141. };
  142. };
  143.  
  144. trips {
  145. cpu_alert0: cpu_alert0 {
  146. /* milliCelsius */
  147. temperature = <75000>;
  148. hysteresis = <2000>;
  149. type = "passive";
  150. };
  151.  
  152. cpu_crit: cpu_crit {
  153. /* milliCelsius */
  154. temperature = <100000>;
  155. hysteresis = <2000>;
  156. type = "critical";
  157. };
  158. };
  159. };
  160. };
  161.  
  162. memory {
  163. reg = <0x40000000 0x80000000>;
  164. };
  165.  
  166. timer {
  167. compatible = "arm,armv7-timer";
  168. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  169. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  170. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  171. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  172. };
  173.  
  174. pmu {
  175. compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  176. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  177. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  178. };
  179.  
  180. clocks {
  181. #address-cells = <1>;
  182. #size-cells = <1>;
  183. ranges;
  184.  
  185. osc24M: clk@1c20050 {
  186. #clock-cells = <0>;
  187. compatible = "fixed-clock";
  188. clock-frequency = <24000000>;
  189. clock-output-names = "osc24M";
  190. };
  191.  
  192. osc32k: clk@0 {
  193. #clock-cells = <0>;
  194. compatible = "fixed-clock";
  195. clock-frequency = <32768>;
  196. clock-output-names = "osc32k";
  197. };
  198.  
  199. /*
  200. * The following two are dummy clocks, placeholders
  201. * used in the gmac_tx clock. The gmac driver will
  202. * choose one parent depending on the PHY interface
  203. * mode, using clk_set_rate auto-reparenting.
  204. *
  205. * The actual TX clock rate is not controlled by the
  206. * gmac_tx clock.
  207. */
  208. mii_phy_tx_clk: clk@1 {
  209. #clock-cells = <0>;
  210. compatible = "fixed-clock";
  211. clock-frequency = <25000000>;
  212. clock-output-names = "mii_phy_tx";
  213. };
  214.  
  215. gmac_int_tx_clk: clk@2 {
  216. #clock-cells = <0>;
  217. compatible = "fixed-clock";
  218. clock-frequency = <125000000>;
  219. clock-output-names = "gmac_int_tx";
  220. };
  221.  
  222. gmac_tx_clk: clk@1c20164 {
  223. #clock-cells = <0>;
  224. compatible = "allwinner,sun7i-a20-gmac-clk";
  225. reg = <0x01c20164 0x4>;
  226. clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
  227. clock-output-names = "gmac_tx";
  228. };
  229. };
  230.  
  231. de: display-engine {
  232. compatible = "allwinner,sun7i-a20-display-engine";
  233. allwinner,pipelines = <&fe0>, <&fe1>;
  234. status = "disabled";
  235. };
  236.  
  237. soc@1c00000 {
  238. compatible = "simple-bus";
  239. #address-cells = <1>;
  240. #size-cells = <1>;
  241. ranges;
  242.  
  243. sram-controller@1c00000 {
  244. compatible = "allwinner,sun4i-a10-sram-controller";
  245. reg = <0x01c00000 0x30>;
  246. #address-cells = <1>;
  247. #size-cells = <1>;
  248. ranges;
  249.  
  250. sram_a: sram@00000000 {
  251. compatible = "mmio-sram";
  252. reg = <0x00000000 0xc000>;
  253. #address-cells = <1>;
  254. #size-cells = <1>;
  255. ranges = <0 0x00000000 0xc000>;
  256.  
  257. emac_sram: sram-section@8000 {
  258. compatible = "allwinner,sun4i-a10-sram-a3-a4";
  259. reg = <0x8000 0x4000>;
  260. status = "disabled";
  261. };
  262. };
  263.  
  264. sram_d: sram@10000 {
  265. compatible = "mmio-sram";
  266. reg = <0x00010000 0x1000>;
  267. #address-cells = <1>;
  268. #size-cells = <1>;
  269. ranges = <0 0x00010000 0x1000>;
  270.  
  271. otg_sram: sram-section@0000 {
  272. compatible = "allwinner,sun4i-a10-sram-d";
  273. reg = <0x0000 0x1000>;
  274. status = "disabled";
  275. };
  276. };
  277. };
  278.  
  279. nmi_intc: interrupt-controller@1c00030 {
  280. compatible = "allwinner,sun7i-a20-sc-nmi";
  281. interrupt-controller;
  282. #interrupt-cells = <2>;
  283. reg = <0x01c00030 0x0c>;
  284. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  285. };
  286.  
  287. dma: dma-controller@1c02000 {
  288. compatible = "allwinner,sun4i-a10-dma";
  289. reg = <0x01c02000 0x1000>;
  290. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  291. clocks = <&ccu CLK_AHB_DMA>;
  292. #dma-cells = <2>;
  293. };
  294.  
  295. nfc: nand@1c03000 {
  296. compatible = "allwinner,sun4i-a10-nand";
  297. reg = <0x01c03000 0x1000>;
  298. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  299. clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
  300. clock-names = "ahb", "mod";
  301. dmas = <&dma SUN4I_DMA_DEDICATED 3>;
  302. dma-names = "rxtx";
  303. status = "disabled";
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. };
  307.  
  308. spi0: spi@1c05000 {
  309. compatible = "allwinner,sun4i-a10-spi";
  310. reg = <0x01c05000 0x1000>;
  311. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  312. clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
  313. clock-names = "ahb", "mod";
  314. dmas = <&dma SUN4I_DMA_DEDICATED 27>,
  315. <&dma SUN4I_DMA_DEDICATED 26>;
  316. dma-names = "rx", "tx";
  317. status = "disabled";
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. num-cs = <4>;
  321. };
  322.  
  323. spi1: spi@1c06000 {
  324. compatible = "allwinner,sun4i-a10-spi";
  325. reg = <0x01c06000 0x1000>;
  326. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  327. clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
  328. clock-names = "ahb", "mod";
  329. dmas = <&dma SUN4I_DMA_DEDICATED 9>,
  330. <&dma SUN4I_DMA_DEDICATED 8>;
  331. dma-names = "rx", "tx";
  332. status = "disabled";
  333. #address-cells = <1>;
  334. #size-cells = <0>;
  335. num-cs = <1>;
  336. };
  337.  
  338. emac: ethernet@1c0b000 {
  339. compatible = "allwinner,sun4i-a10-emac";
  340. reg = <0x01c0b000 0x1000>;
  341. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  342. clocks = <&ccu CLK_AHB_EMAC>;
  343. allwinner,sram = <&emac_sram 1>;
  344. status = "disabled";
  345. };
  346.  
  347. mdio: mdio@1c0b080 {
  348. compatible = "allwinner,sun4i-a10-mdio";
  349. reg = <0x01c0b080 0x14>;
  350. status = "disabled";
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. };
  354.  
  355. tcon0: lcd-controller@1c0c000 {
  356. compatible = "allwinner,sun7i-a20-tcon";
  357. reg = <0x01c0c000 0x1000>;
  358. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  359. resets = <&ccu RST_TCON0>;
  360. reset-names = "lcd";
  361. clocks = <&ccu CLK_AHB_LCD0>,
  362. <&ccu CLK_TCON0_CH0>,
  363. <&ccu CLK_TCON0_CH1>;
  364. clock-names = "ahb",
  365. "tcon-ch0",
  366. "tcon-ch1";
  367. clock-output-names = "tcon0-pixel-clock";
  368. dmas = <&dma SUN4I_DMA_DEDICATED 14>;
  369.  
  370. ports {
  371. #address-cells = <1>;
  372. #size-cells = <0>;
  373.  
  374. tcon0_in: port@0 {
  375. #address-cells = <1>;
  376. #size-cells = <0>;
  377. reg = <0>;
  378.  
  379. tcon0_in_be0: endpoint@0 {
  380. reg = <0>;
  381. remote-endpoint = <&be0_out_tcon0>;
  382. };
  383.  
  384. tcon0_in_be1: endpoint@1 {
  385. reg = <1>;
  386. remote-endpoint = <&be1_out_tcon0>;
  387. };
  388. };
  389.  
  390. tcon0_out: port@1 {
  391. #address-cells = <1>;
  392. #size-cells = <0>;
  393. reg = <1>;
  394.  
  395. tcon0_out_hdmi: endpoint@1 {
  396. reg = <1>;
  397. remote-endpoint = <&hdmi_in_tcon0>;
  398. allwinner,tcon-channel = <1>;
  399. };
  400. };
  401. };
  402. };
  403.  
  404. tcon1: lcd-controller@1c0d000 {
  405. compatible = "allwinner,sun7i-a20-tcon";
  406. reg = <0x01c0d000 0x1000>;
  407. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  408. resets = <&ccu RST_TCON1>;
  409. reset-names = "lcd";
  410. clocks = <&ccu CLK_AHB_LCD1>,
  411. <&ccu CLK_TCON1_CH0>,
  412. <&ccu CLK_TCON1_CH1>;
  413. clock-names = "ahb",
  414. "tcon-ch0",
  415. "tcon-ch1";
  416. clock-output-names = "tcon1-pixel-clock";
  417. dmas = <&dma SUN4I_DMA_DEDICATED 15>;
  418.  
  419. ports {
  420. #address-cells = <1>;
  421. #size-cells = <0>;
  422.  
  423. tcon1_in: port@0 {
  424. #address-cells = <1>;
  425. #size-cells = <0>;
  426. reg = <0>;
  427.  
  428. tcon1_in_be0: endpoint@0 {
  429. reg = <0>;
  430. remote-endpoint = <&be0_out_tcon1>;
  431. };
  432.  
  433. tcon1_in_be1: endpoint@1 {
  434. reg = <1>;
  435. remote-endpoint = <&be1_out_tcon1>;
  436. };
  437. };
  438.  
  439. tcon1_out: port@1 {
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. reg = <1>;
  443.  
  444. tcon1_out_hdmi: endpoint@1 {
  445. reg = <1>;
  446. remote-endpoint = <&hdmi_in_tcon1>;
  447. allwinner,tcon-channel = <1>;
  448. };
  449. };
  450. };
  451. };
  452.  
  453. mmc0: mmc@1c0f000 {
  454. compatible = "allwinner,sun7i-a20-mmc";
  455. reg = <0x01c0f000 0x1000>;
  456. clocks = <&ccu CLK_AHB_MMC0>,
  457. <&ccu CLK_MMC0>,
  458. <&ccu CLK_MMC0_OUTPUT>,
  459. <&ccu CLK_MMC0_SAMPLE>;
  460. clock-names = "ahb",
  461. "mmc",
  462. "output",
  463. "sample";
  464. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  465. status = "disabled";
  466. #address-cells = <1>;
  467. #size-cells = <0>;
  468. };
  469.  
  470. mmc1: mmc@1c10000 {
  471. compatible = "allwinner,sun7i-a20-mmc";
  472. reg = <0x01c10000 0x1000>;
  473. clocks = <&ccu CLK_AHB_MMC1>,
  474. <&ccu CLK_MMC1>,
  475. <&ccu CLK_MMC1_OUTPUT>,
  476. <&ccu CLK_MMC1_SAMPLE>;
  477. clock-names = "ahb",
  478. "mmc",
  479. "output",
  480. "sample";
  481. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  482. status = "disabled";
  483. #address-cells = <1>;
  484. #size-cells = <0>;
  485. };
  486.  
  487. mmc2: mmc@1c11000 {
  488. compatible = "allwinner,sun7i-a20-mmc";
  489. reg = <0x01c11000 0x1000>;
  490. clocks = <&ccu CLK_AHB_MMC2>,
  491. <&ccu CLK_MMC2>,
  492. <&ccu CLK_MMC2_OUTPUT>,
  493. <&ccu CLK_MMC2_SAMPLE>;
  494. clock-names = "ahb",
  495. "mmc",
  496. "output",
  497. "sample";
  498. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  499. status = "disabled";
  500. #address-cells = <1>;
  501. #size-cells = <0>;
  502. };
  503.  
  504. mmc3: mmc@1c12000 {
  505. compatible = "allwinner,sun7i-a20-mmc";
  506. reg = <0x01c12000 0x1000>;
  507. clocks = <&ccu CLK_AHB_MMC3>,
  508. <&ccu CLK_MMC3>,
  509. <&ccu CLK_MMC3_OUTPUT>,
  510. <&ccu CLK_MMC3_SAMPLE>;
  511. clock-names = "ahb",
  512. "mmc",
  513. "output",
  514. "sample";
  515. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  516. status = "disabled";
  517. #address-cells = <1>;
  518. #size-cells = <0>;
  519. };
  520.  
  521. usb_otg: usb@1c13000 {
  522. compatible = "allwinner,sun4i-a10-musb";
  523. reg = <0x01c13000 0x0400>;
  524. clocks = <&ccu CLK_AHB_OTG>;
  525. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  526. interrupt-names = "mc";
  527. phys = <&usbphy 0>;
  528. phy-names = "usb";
  529. extcon = <&usbphy 0>;
  530. allwinner,sram = <&otg_sram 1>;
  531. status = "disabled";
  532. };
  533.  
  534. usbphy: phy@1c13400 {
  535. #phy-cells = <1>;
  536. compatible = "allwinner,sun7i-a20-usb-phy";
  537. reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
  538. reg-names = "phy_ctrl", "pmu1", "pmu2";
  539. clocks = <&ccu CLK_USB_PHY>;
  540. clock-names = "usb_phy";
  541. resets = <&ccu RST_USB_PHY0>,
  542. <&ccu RST_USB_PHY1>,
  543. <&ccu RST_USB_PHY2>;
  544. reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
  545. status = "disabled";
  546. };
  547.  
  548. ehci0: usb@1c14000 {
  549. compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
  550. reg = <0x01c14000 0x100>;
  551. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  552. clocks = <&ccu CLK_AHB_EHCI0>;
  553. phys = <&usbphy 1>;
  554. phy-names = "usb";
  555. status = "disabled";
  556. };
  557.  
  558. ohci0: usb@1c14400 {
  559. compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
  560. reg = <0x01c14400 0x100>;
  561. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  562. clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
  563. phys = <&usbphy 1>;
  564. phy-names = "usb";
  565. status = "disabled";
  566. };
  567.  
  568. crypto: crypto-engine@1c15000 {
  569. compatible = "allwinner,sun7i-a20-crypto",
  570. "allwinner,sun4i-a10-crypto";
  571. reg = <0x01c15000 0x1000>;
  572. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  573. clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
  574. clock-names = "ahb", "mod";
  575. };
  576.  
  577. hdmi: hdmi@1c16000 {
  578. compatible = "allwinner,sun7i-a20-hdmi",
  579. "allwinner,sun5i-a10s-hdmi";
  580. reg = <0x01c16000 0x1000>;
  581. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  582. clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
  583. <&ccu 9>,
  584. <&ccu 18>;
  585. clock-names = "ahb", "mod", "pll-0", "pll-1";
  586. dmas = <&dma SUN4I_DMA_NORMAL 16>,
  587. <&dma SUN4I_DMA_NORMAL 16>,
  588. <&dma SUN4I_DMA_DEDICATED 24>;
  589. dma-names = "ddc-tx", "ddc-rx", "audio-tx";
  590. status = "disabled";
  591.  
  592. ports {
  593. #address-cells = <1>;
  594. #size-cells = <0>;
  595.  
  596. hdmi_in: port@0 {
  597. #address-cells = <1>;
  598. #size-cells = <0>;
  599. reg = <0>;
  600.  
  601. hdmi_in_tcon0: endpoint@0 {
  602. reg = <0>;
  603. remote-endpoint = <&tcon0_out_hdmi>;
  604. };
  605.  
  606. hdmi_in_tcon1: endpoint@1 {
  607. reg = <1>;
  608. remote-endpoint = <&tcon1_out_hdmi>;
  609. };
  610. };
  611.  
  612. hdmi_out: port@1 {
  613. #address-cells = <1>;
  614. #size-cells = <0>;
  615. reg = <1>;
  616. };
  617. };
  618. };
  619.  
  620. spi2: spi@1c17000 {
  621. compatible = "allwinner,sun4i-a10-spi";
  622. reg = <0x01c17000 0x1000>;
  623. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  624. clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
  625. clock-names = "ahb", "mod";
  626. dmas = <&dma SUN4I_DMA_DEDICATED 29>,
  627. <&dma SUN4I_DMA_DEDICATED 28>;
  628. dma-names = "rx", "tx";
  629. status = "disabled";
  630. #address-cells = <1>;
  631. #size-cells = <0>;
  632. num-cs = <1>;
  633. };
  634.  
  635. ahci: sata@1c18000 {
  636. compatible = "allwinner,sun4i-a10-ahci";
  637. reg = <0x01c18000 0x1000>;
  638. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  639. clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
  640. status = "disabled";
  641. };
  642.  
  643. ehci1: usb@1c1c000 {
  644. compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
  645. reg = <0x01c1c000 0x100>;
  646. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  647. clocks = <&ccu CLK_AHB_EHCI1>;
  648. phys = <&usbphy 2>;
  649. phy-names = "usb";
  650. status = "disabled";
  651. };
  652.  
  653. ohci1: usb@1c1c400 {
  654. compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
  655. reg = <0x01c1c400 0x100>;
  656. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  657. clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
  658. phys = <&usbphy 2>;
  659. phy-names = "usb";
  660. status = "disabled";
  661. };
  662.  
  663. spi3: spi@1c1f000 {
  664. compatible = "allwinner,sun4i-a10-spi";
  665. reg = <0x01c1f000 0x1000>;
  666. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  667. clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
  668. clock-names = "ahb", "mod";
  669. dmas = <&dma SUN4I_DMA_DEDICATED 31>,
  670. <&dma SUN4I_DMA_DEDICATED 30>;
  671. dma-names = "rx", "tx";
  672. status = "disabled";
  673. #address-cells = <1>;
  674. #size-cells = <0>;
  675. num-cs = <1>;
  676. };
  677.  
  678. ccu: clock@1c20000 {
  679. compatible = "allwinner,sun7i-a20-ccu";
  680. reg = <0x01c20000 0x400>;
  681. clocks = <&osc24M>, <&osc32k>;
  682. clock-names = "hosc", "losc";
  683. #clock-cells = <1>;
  684. #reset-cells = <1>;
  685. };
  686.  
  687. pio: pinctrl@1c20800 {
  688. compatible = "allwinner,sun7i-a20-pinctrl";
  689. reg = <0x01c20800 0x400>;
  690. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  691. clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
  692. clock-names = "apb", "hosc", "losc";
  693. gpio-controller;
  694. interrupt-controller;
  695. #interrupt-cells = <3>;
  696. #gpio-cells = <3>;
  697.  
  698. can0_pins_a: can0@0 {
  699. pins = "PH20", "PH21";
  700. function = "can";
  701. };
  702.  
  703. clk_out_a_pins_a: clk_out_a@0 {
  704. pins = "PI12";
  705. function = "clk_out_a";
  706. };
  707.  
  708. clk_out_b_pins_a: clk_out_b@0 {
  709. pins = "PI13";
  710. function = "clk_out_b";
  711. };
  712.  
  713. emac_pins_a: emac0@0 {
  714. pins = "PA0", "PA1", "PA2",
  715. "PA3", "PA4", "PA5", "PA6",
  716. "PA7", "PA8", "PA9", "PA10",
  717. "PA11", "PA12", "PA13", "PA14",
  718. "PA15", "PA16";
  719. function = "emac";
  720. };
  721.  
  722. gmac_pins_mii_a: gmac_mii@0 {
  723. pins = "PA0", "PA1", "PA2",
  724. "PA3", "PA4", "PA5", "PA6",
  725. "PA7", "PA8", "PA9", "PA10",
  726. "PA11", "PA12", "PA13", "PA14",
  727. "PA15", "PA16";
  728. function = "gmac";
  729. };
  730.  
  731. gmac_pins_rgmii_a: gmac_rgmii@0 {
  732. pins = "PA0", "PA1", "PA2",
  733. "PA3", "PA4", "PA5", "PA6",
  734. "PA7", "PA8", "PA10",
  735. "PA11", "PA12", "PA13",
  736. "PA15", "PA16";
  737. function = "gmac";
  738. /*
  739. * data lines in RGMII mode use DDR mode
  740. * and need a higher signal drive strength
  741. */
  742. drive-strength = <40>;
  743. };
  744.  
  745. i2c0_pins_a: i2c0@0 {
  746. pins = "PB0", "PB1";
  747. function = "i2c0";
  748. };
  749.  
  750. i2c1_pins_a: i2c1@0 {
  751. pins = "PB18", "PB19";
  752. function = "i2c1";
  753. };
  754.  
  755. i2c2_pins_a: i2c2@0 {
  756. pins = "PB20", "PB21";
  757. function = "i2c2";
  758. };
  759.  
  760. i2c3_pins_a: i2c3@0 {
  761. pins = "PI0", "PI1";
  762. function = "i2c3";
  763. };
  764.  
  765. ir0_rx_pins_a: ir0@0 {
  766. pins = "PB4";
  767. function = "ir0";
  768. };
  769.  
  770. ir0_tx_pins_a: ir0@1 {
  771. pins = "PB3";
  772. function = "ir0";
  773. };
  774.  
  775. ir1_rx_pins_a: ir1@0 {
  776. pins = "PB23";
  777. function = "ir1";
  778. };
  779.  
  780. ir1_tx_pins_a: ir1@1 {
  781. pins = "PB22";
  782. function = "ir1";
  783. };
  784.  
  785. mmc0_pins_a: mmc0@0 {
  786. pins = "PF0", "PF1", "PF2",
  787. "PF3", "PF4", "PF5";
  788. function = "mmc0";
  789. drive-strength = <30>;
  790. bias-pull-up;
  791. };
  792.  
  793. mmc2_pins_a: mmc2@0 {
  794. pins = "PC6", "PC7", "PC8",
  795. "PC9", "PC10", "PC11";
  796. function = "mmc2";
  797. drive-strength = <30>;
  798. bias-pull-up;
  799. };
  800.  
  801. mmc3_pins_a: mmc3@0 {
  802. pins = "PI4", "PI5", "PI6",
  803. "PI7", "PI8", "PI9";
  804. function = "mmc3";
  805. drive-strength = <30>;
  806. bias-pull-up;
  807. };
  808.  
  809. ps20_pins_a: ps20@0 {
  810. pins = "PI20", "PI21";
  811. function = "ps2";
  812. };
  813.  
  814. ps21_pins_a: ps21@0 {
  815. pins = "PH12", "PH13";
  816. function = "ps2";
  817. };
  818.  
  819. pwm0_pins_a: pwm0@0 {
  820. pins = "PB2";
  821. function = "pwm";
  822. };
  823.  
  824. pwm1_pins_a: pwm1@0 {
  825. pins = "PI3";
  826. function = "pwm";
  827. };
  828.  
  829. spdif_tx_pins_a: spdif@0 {
  830. pins = "PB13";
  831. function = "spdif";
  832. bias-pull-up;
  833. };
  834.  
  835. spi0_pins_a: spi0@0 {
  836. pins = "PI11", "PI12", "PI13";
  837. function = "spi0";
  838. };
  839.  
  840. spi0_cs0_pins_a: spi0_cs0@0 {
  841. pins = "PI10";
  842. function = "spi0";
  843. };
  844.  
  845. spi0_cs1_pins_a: spi0_cs1@0 {
  846. pins = "PI14";
  847. function = "spi0";
  848. };
  849.  
  850. spi1_pins_a: spi1@0 {
  851. pins = "PI17", "PI18", "PI19";
  852. function = "spi1";
  853. };
  854.  
  855. spi1_cs0_pins_a: spi1_cs0@0 {
  856. pins = "PI16";
  857. function = "spi1";
  858. };
  859.  
  860. spi2_pins_a: spi2@0 {
  861. pins = "PC20", "PC21", "PC22";
  862. function = "spi2";
  863. };
  864.  
  865. spi2_pins_b: spi2@1 {
  866. pins = "PB15", "PB16", "PB17";
  867. function = "spi2";
  868. };
  869.  
  870. spi2_cs0_pins_a: spi2_cs0@0 {
  871. pins = "PC19";
  872. function = "spi2";
  873. };
  874.  
  875. spi2_cs0_pins_b: spi2_cs0@1 {
  876. pins = "PB14";
  877. function = "spi2";
  878. };
  879.  
  880. uart0_pins_a: uart0@0 {
  881. pins = "PB22", "PB23";
  882. function = "uart0";
  883. };
  884.  
  885. uart2_pins_a: uart2@0 {
  886. pins = "PI16", "PI17", "PI18", "PI19";
  887. function = "uart2";
  888. };
  889.  
  890. uart3_pins_a: uart3@0 {
  891. pins = "PG6", "PG7", "PG8", "PG9";
  892. function = "uart3";
  893. };
  894.  
  895. uart3_pins_b: uart3@1 {
  896. pins = "PH0", "PH1";
  897. function = "uart3";
  898. };
  899.  
  900. uart4_pins_a: uart4@0 {
  901. pins = "PG10", "PG11";
  902. function = "uart4";
  903. };
  904.  
  905. uart4_pins_b: uart4@1 {
  906. pins = "PH4", "PH5";
  907. function = "uart4";
  908. };
  909.  
  910. uart5_pins_a: uart5@0 {
  911. pins = "PI10", "PI11";
  912. function = "uart5";
  913. };
  914.  
  915. uart6_pins_a: uart6@0 {
  916. pins = "PI12", "PI13";
  917. function = "uart6";
  918. };
  919.  
  920. uart7_pins_a: uart7@0 {
  921. pins = "PI20", "PI21";
  922. function = "uart7";
  923. };
  924.  
  925. lcd_rgb888_pins: lcd-rgb888@0 {
  926. pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
  927. "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
  928. "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
  929. "PD24", "PD25", "PD26", "PD27";
  930. function = "lcd0";
  931. };
  932. };
  933.  
  934. timer@1c20c00 {
  935. compatible = "allwinner,sun4i-a10-timer";
  936. reg = <0x01c20c00 0x90>;
  937. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  938. <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  939. <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  940. <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  941. <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  942. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  943. clocks = <&osc24M>;
  944. };
  945.  
  946. wdt: watchdog@1c20c90 {
  947. compatible = "allwinner,sun4i-a10-wdt";
  948. reg = <0x01c20c90 0x10>;
  949. };
  950.  
  951. rtc: rtc@1c20d00 {
  952. compatible = "allwinner,sun7i-a20-rtc";
  953. reg = <0x01c20d00 0x20>;
  954. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  955. };
  956.  
  957. pwm: pwm@1c20e00 {
  958. compatible = "allwinner,sun7i-a20-pwm";
  959. reg = <0x01c20e00 0xc>;
  960. clocks = <&osc24M>;
  961. #pwm-cells = <3>;
  962. status = "disabled";
  963. };
  964.  
  965. spdif: spdif@1c21000 {
  966. #sound-dai-cells = <0>;
  967. compatible = "allwinner,sun4i-a10-spdif";
  968. reg = <0x01c21000 0x400>;
  969. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  970. clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
  971. clock-names = "apb", "spdif";
  972. dmas = <&dma SUN4I_DMA_NORMAL 2>,
  973. <&dma SUN4I_DMA_NORMAL 2>;
  974. dma-names = "rx", "tx";
  975. status = "disabled";
  976. };
  977.  
  978. ir0: ir@1c21800 {
  979. compatible = "allwinner,sun4i-a10-ir";
  980. clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
  981. clock-names = "apb", "ir";
  982. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  983. reg = <0x01c21800 0x40>;
  984. status = "disabled";
  985. };
  986.  
  987. ir1: ir@1c21c00 {
  988. compatible = "allwinner,sun4i-a10-ir";
  989. clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
  990. clock-names = "apb", "ir";
  991. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  992. reg = <0x01c21c00 0x40>;
  993. status = "disabled";
  994. };
  995.  
  996. i2s1: i2s@1c22000 {
  997. #sound-dai-cells = <0>;
  998. compatible = "allwinner,sun4i-a10-i2s";
  999. reg = <0x01c22000 0x400>;
  1000. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  1001. clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
  1002. clock-names = "apb", "mod";
  1003. dmas = <&dma SUN4I_DMA_NORMAL 4>,
  1004. <&dma SUN4I_DMA_NORMAL 4>;
  1005. dma-names = "rx", "tx";
  1006. status = "disabled";
  1007. };
  1008.  
  1009. i2s0: i2s@1c22400 {
  1010. #sound-dai-cells = <0>;
  1011. compatible = "allwinner,sun4i-a10-i2s";
  1012. reg = <0x01c22400 0x400>;
  1013. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  1014. clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
  1015. clock-names = "apb", "mod";
  1016. dmas = <&dma SUN4I_DMA_NORMAL 3>,
  1017. <&dma SUN4I_DMA_NORMAL 3>;
  1018. dma-names = "rx", "tx";
  1019. status = "disabled";
  1020. };
  1021.  
  1022. lradc: lradc@1c22800 {
  1023. compatible = "allwinner,sun4i-a10-lradc-keys";
  1024. reg = <0x01c22800 0x100>;
  1025. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  1026. status = "disabled";
  1027. };
  1028.  
  1029. codec: codec@1c22c00 {
  1030. #sound-dai-cells = <0>;
  1031. compatible = "allwinner,sun7i-a20-codec";
  1032. reg = <0x01c22c00 0x40>;
  1033. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1034. clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
  1035. clock-names = "apb", "codec";
  1036. dmas = <&dma SUN4I_DMA_NORMAL 19>,
  1037. <&dma SUN4I_DMA_NORMAL 19>;
  1038. dma-names = "rx", "tx";
  1039. status = "disabled";
  1040. };
  1041.  
  1042. sid: eeprom@1c23800 {
  1043. compatible = "allwinner,sun7i-a20-sid";
  1044. reg = <0x01c23800 0x200>;
  1045. };
  1046.  
  1047. i2s2: i2s@1c24400 {
  1048. #sound-dai-cells = <0>;
  1049. compatible = "allwinner,sun4i-a10-i2s";
  1050. reg = <0x01c24400 0x400>;
  1051. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  1052. clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
  1053. clock-names = "apb", "mod";
  1054. dmas = <&dma SUN4I_DMA_NORMAL 6>,
  1055. <&dma SUN4I_DMA_NORMAL 6>;
  1056. dma-names = "rx", "tx";
  1057. status = "disabled";
  1058. };
  1059.  
  1060. rtp: rtp@1c25000 {
  1061. compatible = "allwinner,sun5i-a13-ts";
  1062. reg = <0x01c25000 0x100>;
  1063. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  1064. #thermal-sensor-cells = <0>;
  1065. };
  1066.  
  1067. uart0: serial@1c28000 {
  1068. compatible = "snps,dw-apb-uart";
  1069. reg = <0x01c28000 0x400>;
  1070. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  1071. reg-shift = <2>;
  1072. reg-io-width = <4>;
  1073. clocks = <&ccu CLK_APB1_UART0>;
  1074. status = "disabled";
  1075. };
  1076.  
  1077. uart1: serial@1c28400 {
  1078. compatible = "snps,dw-apb-uart";
  1079. reg = <0x01c28400 0x400>;
  1080. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  1081. reg-shift = <2>;
  1082. reg-io-width = <4>;
  1083. clocks = <&ccu CLK_APB1_UART1>;
  1084. status = "disabled";
  1085. };
  1086.  
  1087. uart2: serial@1c28800 {
  1088. compatible = "snps,dw-apb-uart";
  1089. reg = <0x01c28800 0x400>;
  1090. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  1091. reg-shift = <2>;
  1092. reg-io-width = <4>;
  1093. clocks = <&ccu CLK_APB1_UART2>;
  1094. status = "disabled";
  1095. };
  1096.  
  1097. uart3: serial@1c28c00 {
  1098. compatible = "snps,dw-apb-uart";
  1099. reg = <0x01c28c00 0x400>;
  1100. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  1101. reg-shift = <2>;
  1102. reg-io-width = <4>;
  1103. clocks = <&ccu CLK_APB1_UART3>;
  1104. status = "disabled";
  1105. };
  1106.  
  1107. uart4: serial@1c29000 {
  1108. compatible = "snps,dw-apb-uart";
  1109. reg = <0x01c29000 0x400>;
  1110. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  1111. reg-shift = <2>;
  1112. reg-io-width = <4>;
  1113. clocks = <&ccu CLK_APB1_UART4>;
  1114. status = "disabled";
  1115. };
  1116.  
  1117. uart5: serial@1c29400 {
  1118. compatible = "snps,dw-apb-uart";
  1119. reg = <0x01c29400 0x400>;
  1120. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  1121. reg-shift = <2>;
  1122. reg-io-width = <4>;
  1123. clocks = <&ccu CLK_APB1_UART5>;
  1124. status = "disabled";
  1125. };
  1126.  
  1127. uart6: serial@1c29800 {
  1128. compatible = "snps,dw-apb-uart";
  1129. reg = <0x01c29800 0x400>;
  1130. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  1131. reg-shift = <2>;
  1132. reg-io-width = <4>;
  1133. clocks = <&ccu CLK_APB1_UART6>;
  1134. status = "disabled";
  1135. };
  1136.  
  1137. uart7: serial@1c29c00 {
  1138. compatible = "snps,dw-apb-uart";
  1139. reg = <0x01c29c00 0x400>;
  1140. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  1141. reg-shift = <2>;
  1142. reg-io-width = <4>;
  1143. clocks = <&ccu CLK_APB1_UART7>;
  1144. status = "disabled";
  1145. };
  1146.  
  1147. ps20: ps2@1c2a000 {
  1148. compatible = "allwinner,sun4i-a10-ps2";
  1149. reg = <0x01c2a000 0x400>;
  1150. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  1151. clocks = <&ccu CLK_APB1_PS20>;
  1152. status = "disabled";
  1153. };
  1154.  
  1155. ps21: ps2@1c2a400 {
  1156. compatible = "allwinner,sun4i-a10-ps2";
  1157. reg = <0x01c2a400 0x400>;
  1158. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  1159. clocks = <&ccu CLK_APB1_PS21>;
  1160. status = "disabled";
  1161. };
  1162.  
  1163. i2c0: i2c@1c2ac00 {
  1164. compatible = "allwinner,sun7i-a20-i2c",
  1165. "allwinner,sun4i-a10-i2c";
  1166. reg = <0x01c2ac00 0x400>;
  1167. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  1168. clocks = <&ccu CLK_APB1_I2C0>;
  1169. status = "disabled";
  1170. #address-cells = <1>;
  1171. #size-cells = <0>;
  1172. };
  1173.  
  1174. i2c1: i2c@1c2b000 {
  1175. compatible = "allwinner,sun7i-a20-i2c",
  1176. "allwinner,sun4i-a10-i2c";
  1177. reg = <0x01c2b000 0x400>;
  1178. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  1179. clocks = <&ccu CLK_APB1_I2C1>;
  1180. status = "disabled";
  1181. #address-cells = <1>;
  1182. #size-cells = <0>;
  1183. };
  1184.  
  1185. i2c2: i2c@1c2b400 {
  1186. compatible = "allwinner,sun7i-a20-i2c",
  1187. "allwinner,sun4i-a10-i2c";
  1188. reg = <0x01c2b400 0x400>;
  1189. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1190. clocks = <&ccu CLK_APB1_I2C2>;
  1191. status = "disabled";
  1192. #address-cells = <1>;
  1193. #size-cells = <0>;
  1194. };
  1195.  
  1196. i2c3: i2c@1c2b800 {
  1197. compatible = "allwinner,sun7i-a20-i2c",
  1198. "allwinner,sun4i-a10-i2c";
  1199. reg = <0x01c2b800 0x400>;
  1200. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  1201. clocks = <&ccu CLK_APB1_I2C3>;
  1202. status = "disabled";
  1203. #address-cells = <1>;
  1204. #size-cells = <0>;
  1205. };
  1206.  
  1207. can0: can@1c2bc00 {
  1208. compatible = "allwinner,sun7i-a20-can",
  1209. "allwinner,sun4i-a10-can";
  1210. reg = <0x01c2bc00 0x400>;
  1211. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  1212. clocks = <&ccu CLK_APB1_CAN>;
  1213. status = "disabled";
  1214. };
  1215.  
  1216. i2c4: i2c@1c2c000 {
  1217. compatible = "allwinner,sun7i-a20-i2c",
  1218. "allwinner,sun4i-a10-i2c";
  1219. reg = <0x01c2c000 0x400>;
  1220. interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  1221. clocks = <&ccu CLK_APB1_I2C4>;
  1222. status = "disabled";
  1223. #address-cells = <1>;
  1224. #size-cells = <0>;
  1225. };
  1226.  
  1227. mali: gpu@1c40000 {
  1228. compatible = "allwinner,sun8i-a23-mali",
  1229. "allwinner,sun7i-a20-mali", "arm,mali-400";
  1230. reg = <0x01c40000 0x10000>;
  1231. interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
  1232. <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
  1233. <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
  1234. <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  1235. <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
  1236. <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
  1237. <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  1238. interrupt-names = "gp",
  1239. "gpmmu",
  1240. "pp0",
  1241. "ppmmu0",
  1242. "pp1",
  1243. "ppmmu1",
  1244. "pmu";
  1245. clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
  1246. clock-names = "bus", "core";
  1247. resets = <&ccu RST_GPU>;
  1248. #cooling-cells = <2>;
  1249.  
  1250. assigned-clocks = <&ccu CLK_GPU>;
  1251. assigned-clock-rates = <381000000>;
  1252. };
  1253.  
  1254. gmac: ethernet@1c50000 {
  1255. compatible = "allwinner,sun7i-a20-gmac";
  1256. reg = <0x01c50000 0x10000>;
  1257. interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  1258. interrupt-names = "macirq";
  1259. clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
  1260. clock-names = "stmmaceth", "allwinner_gmac_tx";
  1261. snps,pbl = <2>;
  1262. snps,fixed-burst;
  1263. snps,force_sf_dma_mode;
  1264. status = "disabled";
  1265. #address-cells = <1>;
  1266. #size-cells = <0>;
  1267. };
  1268.  
  1269. hstimer@1c60000 {
  1270. compatible = "allwinner,sun7i-a20-hstimer";
  1271. reg = <0x01c60000 0x1000>;
  1272. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  1273. <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  1274. <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  1275. <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  1276. clocks = <&ccu CLK_AHB_HSTIMER>;
  1277. };
  1278.  
  1279. gic: interrupt-controller@1c81000 {
  1280. compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  1281. reg = <0x01c81000 0x1000>,
  1282. <0x01c82000 0x2000>,
  1283. <0x01c84000 0x2000>,
  1284. <0x01c86000 0x2000>;
  1285. interrupt-controller;
  1286. #interrupt-cells = <3>;
  1287. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  1288. };
  1289.  
  1290. fe0: display-frontend@1e00000 {
  1291. compatible = "allwinner,sun7i-a20-display-frontend";
  1292. reg = <0x01e00000 0x20000>;
  1293. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  1294. clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
  1295. <&ccu CLK_DRAM_DE_FE0>;
  1296. clock-names = "ahb", "mod",
  1297. "ram";
  1298. resets = <&ccu RST_DE_FE0>;
  1299.  
  1300. ports {
  1301. #address-cells = <1>;
  1302. #size-cells = <0>;
  1303.  
  1304. fe0_out: port@1 {
  1305. #address-cells = <1>;
  1306. #size-cells = <0>;
  1307. reg = <1>;
  1308.  
  1309. fe0_out_be0: endpoint@0 {
  1310. reg = <0>;
  1311. remote-endpoint = <&be0_in_fe0>;
  1312. };
  1313.  
  1314. fe0_out_be1: endpoint@1 {
  1315. reg = <1>;
  1316. remote-endpoint = <&be1_in_fe0>;
  1317. };
  1318. };
  1319. };
  1320. };
  1321.  
  1322. fe1: display-frontend@1e20000 {
  1323. compatible = "allwinner,sun7i-a20-display-frontend";
  1324. reg = <0x01e20000 0x20000>;
  1325. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  1326. clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
  1327. <&ccu CLK_DRAM_DE_FE1>;
  1328. clock-names = "ahb", "mod",
  1329. "ram";
  1330. resets = <&ccu RST_DE_FE1>;
  1331.  
  1332. ports {
  1333. #address-cells = <1>;
  1334. #size-cells = <0>;
  1335.  
  1336. fe1_out: port@1 {
  1337. #address-cells = <1>;
  1338. #size-cells = <0>;
  1339. reg = <1>;
  1340.  
  1341. fe1_out_be0: endpoint@0 {
  1342. reg = <0>;
  1343. remote-endpoint = <&be0_in_fe1>;
  1344. };
  1345.  
  1346. fe1_out_be1: endpoint@1 {
  1347. reg = <1>;
  1348. remote-endpoint = <&be1_in_fe1>;
  1349. };
  1350. };
  1351. };
  1352. };
  1353.  
  1354. be1: display-backend@1e40000 {
  1355. compatible = "allwinner,sun7i-a20-display-backend";
  1356. reg = <0x01e40000 0x10000>;
  1357. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  1358. clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
  1359. <&ccu CLK_DRAM_DE_BE1>;
  1360. clock-names = "ahb", "mod",
  1361. "ram";
  1362. resets = <&ccu RST_DE_BE1>;
  1363.  
  1364. ports {
  1365. #address-cells = <1>;
  1366. #size-cells = <0>;
  1367.  
  1368. be1_in: port@0 {
  1369. #address-cells = <1>;
  1370. #size-cells = <0>;
  1371. reg = <0>;
  1372.  
  1373. be1_in_fe0: endpoint@0 {
  1374. reg = <0>;
  1375. remote-endpoint = <&fe0_out_be1>;
  1376. };
  1377.  
  1378. be1_in_fe1: endpoint@1 {
  1379. reg = <1>;
  1380. remote-endpoint = <&fe1_out_be1>;
  1381. };
  1382. };
  1383.  
  1384. be1_out: port@1 {
  1385. #address-cells = <1>;
  1386. #size-cells = <0>;
  1387. reg = <1>;
  1388.  
  1389. be1_out_tcon0: endpoint@0 {
  1390. reg = <0>;
  1391. remote-endpoint = <&tcon1_in_be0>;
  1392. };
  1393.  
  1394. be1_out_tcon1: endpoint@1 {
  1395. reg = <1>;
  1396. remote-endpoint = <&tcon1_in_be1>;
  1397. };
  1398. };
  1399. };
  1400. };
  1401.  
  1402. be0: display-backend@1e60000 {
  1403. compatible = "allwinner,sun7i-a20-display-backend";
  1404. reg = <0x01e60000 0x10000>;
  1405. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  1406. clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  1407. <&ccu CLK_DRAM_DE_BE0>;
  1408. clock-names = "ahb", "mod",
  1409. "ram";
  1410. resets = <&ccu RST_DE_BE0>;
  1411.  
  1412. ports {
  1413. #address-cells = <1>;
  1414. #size-cells = <0>;
  1415.  
  1416. be0_in: port@0 {
  1417. #address-cells = <1>;
  1418. #size-cells = <0>;
  1419. reg = <0>;
  1420.  
  1421. be0_in_fe0: endpoint@0 {
  1422. reg = <0>;
  1423. remote-endpoint = <&fe0_out_be0>;
  1424. };
  1425.  
  1426. be0_in_fe1: endpoint@1 {
  1427. reg = <1>;
  1428. remote-endpoint = <&fe1_out_be0>;
  1429. };
  1430. };
  1431.  
  1432. be0_out: port@1 {
  1433. #address-cells = <1>;
  1434. #size-cells = <0>;
  1435. reg = <1>;
  1436.  
  1437. be0_out_tcon0: endpoint@0 {
  1438. reg = <0>;
  1439. remote-endpoint = <&tcon0_in_be0>;
  1440. };
  1441.  
  1442. be0_out_tcon1: endpoint@1 {
  1443. reg = <1>;
  1444. remote-endpoint = <&tcon1_in_be0>;
  1445. };
  1446. };
  1447. };
  1448. };
  1449. };
  1450. };
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