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Sep 21st, 2019
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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3. ENTITY rstr IS
  4. PORT( s : IN std_logic; r : IN std_logic;
  5. q : INOUT std_logic;
  6. 154
  7. qb : INOUT std_logic ); END rstr;
  8. ARCHITECTURE behav OF rstr IS
  9. COMPONENT notand -- описание используемого компонента PORT( a : IN std_logic;
  10. b : IN std_logic;
  11. c : INOUT std_logic);
  12. END COMPONENT;
  13. BEGIN
  14. u1: notand -- указание u1, как компонента notand
  15. PORT MAP ( s, qb, q); -- указание входов и выхода для u1 u2: notand
  16. PORT MAP (q, r, qb);
  17. END behav;
  18. CONFIGURATION con OF rstr IS
  19. FOR behav
  20. FOR u1, u2: notand
  21. USE ENTITY work.notand (behavior); -- определяет интерфейс END FOR; -- и модель компонента notand
  22. END FOR;
  23. END con;
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