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Oct 15th, 2019
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  1. /*.equ delayCnt = 15
  2.  
  3. .def tmp = r16
  4.  
  5. .cseg
  6. rjmp reset
  7.  
  8. reset:
  9. ldi tmp, high(RAMEND)
  10. out SPH, tmp
  11. ldi tmp, low(RAMEND)
  12. out SPL, tmp
  13.  
  14. ldi tmp, 0xff
  15. out DDRA, tmp
  16. out PORTA, tmp
  17.  
  18. clc
  19.  
  20. main:
  21. rcall aktivnost
  22. rcall delay
  23. rjmp main
  24.  
  25. aktivnost:
  26. in tmp, PORTA
  27. rol tmp
  28. out PORTA, tmp
  29. ret
  30.  
  31. delay:
  32. push r17
  33. push r18
  34. push r19
  35.  
  36. clr r17
  37. clr r18
  38. ldi r19, delayCnt
  39.  
  40. delay_loop:
  41. dec r17
  42. brne delay_loop
  43. dec r18
  44. brne delay_loop
  45. dec r19
  46. brne delay_loop
  47.  
  48. pop r19
  49. pop r18
  50. pop r17
  51. ret*/
  52.  
  53. .equ delayCnt = 9
  54.  
  55. .def tmp = r16
  56.  
  57. .cseg
  58. rjmp reset
  59.  
  60. reset:
  61. ldi tmp, high(RAMEND)
  62. out SPH, tmp
  63. ldi tmp, low(RAMEND)
  64. out SPL, tmp
  65.  
  66. ldi tmp, 0xff
  67. out DDRA, tmp
  68. out PORTA, tmp
  69.  
  70. main:
  71. rcall aktivnost
  72. rcall delay
  73. rjmp main
  74.  
  75. aktivnost:
  76. in tmp, PORTA
  77. cpi tmp, 0x00
  78. breq resetleds
  79. clc
  80. ror tmp
  81. rjmp end
  82. resetleds:
  83. ldi tmp, 0xff
  84. end:
  85. out PORTA, tmp
  86. /*in tmp, PORTA
  87. rol tmp
  88. out PORTA, tmp*/
  89. ret
  90.  
  91. delay:
  92. push r17
  93. push r18
  94. push r19
  95.  
  96. clr r17
  97. clr r18
  98. ldi r19, delayCnt
  99.  
  100. delay_loop:
  101. dec r17
  102. brne delay_loop
  103. dec r18
  104. brne delay_loop
  105. dec r19
  106. brne delay_loop
  107.  
  108. pop r19
  109. pop r18
  110. pop r17
  111. ret
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