ac1

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-- Company:
-- Engineer:
--
-- Create Date: 02/25/2020 02:09:00 PM
-- Design Name:
-- Module Name: p1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity p1 is
    Port ( clk : in STD_LOGIC;
           btn: in  STD_LOGIC_VECTOR (4 downto 0);
           sw:  in  STD_LOGIC_VECTOR (15 downto 0);
           led: out STD_LOGIC_VECTOR (15 downto 0);
           an:  out STD_LOGIC_VECTOR (3 downto 0);
           cat: out STD_LOGIC_VECTOR (6 downto 0));
end p1;

architecture Behavioral of p1 is
 signal count: STD_LOGIC_VECTOR (15 downto 0);
begin
    led<=count;
    an<=btn(3 downto 0);
    cat<=(others=>'0');
process (clk)
begin
   if clk='1' and clk'event then
   if btn="1000" then
      if sw="1000000000000000" then
         count <= count + 1;
      else
         count <= count - 1;
         end if;
      end if;
   end if;
end process;



end Behavioral;