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ac1

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 02/25/2020 02:09:00 PM
  6. -- Design Name:
  7. -- Module Name: p1 - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24. use IEEE.STD_LOGIC_ARITH.ALL;
  25. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  26.  
  27. -- Uncomment the following library declaration if using
  28. -- arithmetic functions with Signed or Unsigned values
  29. --use IEEE.NUMERIC_STD.ALL;
  30.  
  31. -- Uncomment the following library declaration if instantiating
  32. -- any Xilinx leaf cells in this code.
  33. --library UNISIM;
  34. --use UNISIM.VComponents.all;
  35.  
  36. entity p1 is
  37.     Port ( clk : in STD_LOGIC;
  38.            btn: in  STD_LOGIC_VECTOR (4 downto 0);
  39.            sw:  in  STD_LOGIC_VECTOR (15 downto 0);
  40.            led: out STD_LOGIC_VECTOR (15 downto 0);
  41.            an:  out STD_LOGIC_VECTOR (3 downto 0);
  42.            cat: out STD_LOGIC_VECTOR (6 downto 0));
  43. end p1;
  44.  
  45. architecture Behavioral of p1 is
  46.  signal count: STD_LOGIC_VECTOR (15 downto 0);
  47. begin
  48.     led<=count;
  49.     an<=btn(3 downto 0);
  50.     cat<=(others=>'0');
  51. process (clk)
  52. begin
  53.    if clk='1' and clk'event then
  54.    if btn="1000" then
  55.       if sw="1000000000000000" then
  56.          count <= count + 1;
  57.       else
  58.          count <= count - 1;
  59.          end if;
  60.       end if;
  61.    end if;
  62. end process;
  63.  
  64.  
  65.  
  66. end Behavioral;
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